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PDF ( 数据手册 , 数据表 ) ISL97635

零件编号 ISL97635
描述 SMBus 8-Channel LED Driver
制造商 Intersil Corporation
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ISL97635 数据手册, 描述, 功能
®
Data Sheet
December 22, 2008
ISL97635
FN6434.2
SMBus 8-Channel LED Driver
The ISL97635 is a digitally controlled LED driver that
controls 8 channels of LED current for LCD backlight
applications. The ISL97635 is capable of driving typically 72
(8x9) pieces of 3.5V/30mA or 80 (8x10) pieces of
3.2V/20mA LEDs. The ISL97635’s 8 channels of voltage
controlled current sources with typical currents matching of
±1%, which compensate for the non-uniformity effect of
forward voltages variance in the LED stacks. To minimize the
voltage headroom and power loss in the typical multi-strings
operation, the ISL97635 features a dynamic headroom
control that monitors the highest LED forward voltage string
and uses its feedback signal for output regulation.
The LED dimming control can be achieved through a
SMBus, an external PWM, or a variable DC (analog light
sensor) input. SMBus controlled dimming allows 256 levels
each of PWM and DC current adjustments. The SMBus
PWM dimming frequency can be adjusted from 100Hz to
5kHz by an external capacitor. External PWM input allows up
to 20kHz audio noise free PWM dimming. The SMBus PWM
setting and an external PWMI signal can also be combined
to provide a dynamic PWM dimming that complies with
Intel’s DPST (Display Power Saving Technology)
requirement.
One or more channels can be selected sequentially in any
order, allowing scrolling in RGB LED backlighting
applications.
The ISL97635 features extensive protection functions that
include string open and short circuit detections, OVP, OTP,
thermal shutdown and an optional input overcurrent
protection with master fault disconnect switch. The fault
conditions will be recorded in the Fault/Status register. There
are selectable short-circuit thresholds and the switching
frequency can be programmed between 600kHz and
1.2MHz.
Available in the 24 Ld 4mmx4mm QFN, the ISL97635
operates from -40°C to +85°C with input voltage ranging
from 6V to 24V.
Features
• 8 Channels
• 6V to 24V Input
• 34.5V Output Max
• Drive Maximally 72 (3.5V/30mA each) or 80 (3.2V/20mA
each) LEDs
• Current Matching ±1% Typ
• Dynamic Headroom Control
• Dimming Controls
- SMBus 8-Bit PWM Current Control
- SMBus 8-Bit DC Current Control
- External PWM Input up to 20kHz Dimming
- SMBus and External PWM DPST Dimming Control
- DC-to-PWM Dimming Control
• Protections
- String Open Circuit Detection
- String Short Circuit Detection with Selectable Thresholds
- Over-Temperature Protection
- Overvoltage Protection
- Input Overcurrent Protection with Disconnect Switch
• 600kHz/1.2MHz Selectable fSW
• Selectable Channels Allows Scrolling Backlight
• 24 Ld (4mmx4mm) QFN Package
• Pb-Free (RoHS compliant)
Applications
• Notebook Displays WLED or RGB LED Backlighting
• LCD Monitor LED Backlighting
• Automotive Displays LED Backlighting
• Automotive or Traffic Lighting
Ordering Information
PART NUMBER
PART
(Note)
MARKING
ISL97635IRZ* 976 35IRZ
PACKAGE
(Pb-free)
24 Ld 4x4 QFN
PKG.
DWG. #
L24.4x4D
*Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.







ISL97635 pdf, 数据表
ISL97635
Typical Performance Curves (Continued)
2.0
1.5
12V/1mA
1.0 12V/20mA
0.5
0.0
-0.5 6V/20mA
-1.0 6V/1mA
-1.5
-2.0
CH 0 CH 1 CH 2 CH 3 CH 4 CH 5 CH 6 CH 7
CHANNELS
FIGURE 6. CHANNEL-TO-CHANNEL CURRENT MATCHING
1.0
1kHz
0.9
100kHz
20kHz
0.8
VIN = 12V
0.7
200kHz
0.6
10kHz
0.5
0
10 20 30 40 50 60 70 80 90 100
PWM DUTY CYCLE (%)
FIGURE 7. CURRENT MATCHING vs DUTY CYCLE vs
DIMMING FREQUENCY
180
8 CHANNELS
160 9 LEDS PER CHANNEL
VIN = 6V
140 VIN = 12V
120
100
80
60
40
20 VIN = 18V
0
0 10 20 30 40 50 60 70 80 90 100
PWM DUTY CYCLE (%)
FIGURE 8. PWM DIMMING LINEARITY
FIGURE 9. LX, VIIN, IL AND IO AT PWM DIMMING
FIGURE 10. IL AT 50% PWM DIMMING
8
FIGURE 11. IL ZOOM IN AT PWM DIMMING ZOOM IN
FN6434.2
December 22, 2008







ISL97635 equivalent, schematic
ISL97635
TABLE 1. PROTECTIONS TABLE
CASE FAILURE MODE DETECTION MODE
FAILED CHANNEL ACTION
VOUT
GOOD CHANNELS ACTION REGULATED BY
1 CH0 Short Circuit Upper
CH0 ON and burns power
Over-Temperature
Protection limit (OTP)
not triggered and VIIN0
< VSC
CH1 through CH7 Normal
Highest VF of
CH1 through CH7
2 CH0 Short Circuit Upper OTP triggered but CH0 goes off until chip cooled and Same as CH0
VIN0 < VSC
then comes back on with current
reduced to 76%. Further OTP
triggers result in reduction to 53%,
then 30%. Thermal event reported
in Fault/Status Register.
Highest VF of
CH1 through CH7
3 CH0 Short Circuit Upper OTP not triggered CH0 doubled after 6ms time-out. CH1 through CH7 Normal
but VIIN0 > VSC
Time-out reduced to 420µs if above
lower OTP limit
Highest VF of
CH1 through CH7
4 CH0 Open Circuit Upper OTP not triggered VOUT will ramp to OVP. CH0 will CH1 through CH7 Normal
with infinite
and VIIN0 < VSC
time-out after 6ms (800µs if above
resistance
lower OTP limit) and switch off.
VOUT will drop to normal level.
5 CH0 LED Open
Circuit but has
paralleled Zener
Upper OTP not triggered CH0 remains ON and has highest CH1 through CH7 ON, Q1
and VIIN0 < VSC
VF, thus VOUT increases
through Q7 burn power
Highest VF of
CH1 through CH7
VF of CH0
6 CH0 LED Open
Circuit but has
paralleled Zener
Upper OTP triggered but
VIIN0 < VSC
CH0 goes off until chip cooled and
then comes back on with current
reduced to 76%. Further OTP
triggers result in reduction to 53%,
then 30%. Thermal event reported
in Fault/Status Register.
Same as CH0
VF of CH0
7 CH0 LED Open
Circuit but has
paralleled Zener
Upper OTP not triggered CH0 OFF
but VIIN0 > VSC
CH1 through CH7 Normal
Highest VF of
CH1 through CH7
Upper OTP not triggered CH0 remains ON and has highest
but VIINx > VSC
VF, thus VOUT increases.
VOUT increases then CH-X
switches OFF. This is an
unwanted shut off and can be
prevented by setting OVP and/or
VSC at an appropriate level.
VF of CH0
8 Channel-to-Channel Lower OTP triggered but Any channel at below 50% of the target current will fault out after
ΔVF too high
VIINx < VSC
400µs.
Remaining channels driven with normal current.
Highest VF of
CH0 through CH7
9 Channel-to-Channel Upper OTP triggered but All channels switched off until chip cooled and then comes back on Highest VF of
ΔVF too high
VIINx < VSC
with current reduced to 76%. Further OTP triggers result in reduction CH0 through CH7
to 53%, then 30%. Thermal event reported in Fault/Status Register.
10 Output LED stack
voltage too high
VOUT > VOVP
Driven with normal current. Any channel that is below 50% of the target Highest VF of
current will time-out after 6ms.
CH0 through CH7
11 VOUT/LX shorted to LX current and timing Fault switch disabled and system shutdown until fault goes away,
GND
are monitored.
VOUT is checked at start-up with a low current from LX to check for
presence of short before the fault switch is enabled.
OVP pin monitored for
excursions below 20% of
OVP threshold
16 FN6434.2
December 22, 2008










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