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PDF ( 数据手册 , 数据表 ) W83194BR-603

零件编号 W83194BR-603
描述 Clock Generator
制造商 Winbond
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W83194BR-603 数据手册, 描述, 功能
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W83194BR-603
W83194BG-603
Winbond Clock Generator For
INTEL P4 Springdale Series Chipset
Date: Mar/23/2006
Revision: 0.7







W83194BR-603 pdf, 数据表
W83194BR-603/W83194BG-603
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
CPU, SRC, 3V66 and PCI Clock Outputs, continued
PIN PIN NAME
8 PCI_F1
FS4&
9 PCI_F2
12 PCI0
MODE&
13,14,15,18 PCI [1:5]
,19
TYPE
DESCRIPTION
OUT 3.3V PCI free running clock output.
INtd120k Latched input for FS4 at initial power up for H/W selecting
the output frequency, This is internal 120K pull down.
OUT 3.3V PCI free running clock output.
OUT 3.3V PCI clock output.
INtd120k Latched input for pin 30 at initial power up selecting the
0=3V66 clock output, 1=RESET# control pin. This is internal
120KΩ pull down.
OUT Low skew (< 250ps) 3.3V PCI clock outputs.
5.3 Fixed Frequency Outputs
PIN PIN NAME
1 REF0
FS1*
TYPE
OUT
INtp120k
2 REF1
FS0&
22 48MHz
FS3&
21 24_48MHz
OUT
INtd120k
OUT
INtd120k
OUT
SEL24_48#&
INtd120k
DESCRIPTION
14.318MHz output.
Latched input for FS1 at initial power up for H/W selecting
the output frequency. This is internal 120K pull up.
14.318MHz output.
Latched input for FS0 at initial power up for H/W selecting
the output frequency. This is internal 120K pull down.
48MHz clock output for USB.
Latched input for FS3 at initial power up for H/W selecting
the output frequency. This is internal 120K pull down.
24MHz or 48MHz(default) clock output, In power on reset
period, it is a hardware-latched pin, and it can be R/W by
I2C control after power on reset period. Select by register 5
bit 7.
Latched input for 24MHz or 48MHz select pin. This is
internal 120K pull down default 48MHz. In power on reset
period, it is a hardware-latched pin, and it can be R/W by
I2C control after power on reset period. Select by register 5
bit 7.
5.4 I2C Control Interface
PIN PIN NAME
32 SDATA*
31 SCLK*
TYPE
I/OD
IN
DESCRIPTION
Serial data of I2C 2-wire control interface with internal pull-
up resistor.
Serial clock of I2C 2-wire control interface with internal pull-
up resistor.
-4-







W83194BR-603 equivalent, schematic
W83194BR-603/W83194BG-603
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.13 Register 12: Divisor and Step-less Enable Control Register: (Default: FBh)
BIT NAME PWD
DESCRIPTION
7 Reserved
1 Reserved
6 DS9
5 DS5
1 Define the 3V66 divider ratio
1 Table-2 integrate the all divider configuration
4 Reserved
1 Reserved
3 Reserved
1
2 DS2
1 DS1
0 Define the CPU divider ratio
1 Refer to Table-2
0 DS0
1
Table-2 CPU, 3V66 divider ratio selection Table
LSB
3V66
Bit5
MSB
01
Bit2/
0
Div6
Div7
Bit9 1
Div10
Div12
00
Div2
Div8
CPU
Bit1, 0
01 10
Div3
Div4
Div8
Div8
11
Div6
Div8
7.14 Register 13: Divisor and Step-less Enable Control Register (Default: 0Fh)
BIT NAME PWD
DESCRIPTION
7 EN_MN_PROG
6 Reserved
5 Reserved
4 Reserved
0 0: Output frequency depend on frequency table
1: Program all clock frequency by changing M/N value
The equation is
VCO =14.318MHz*(N+4)/ M.
Once the watchdog timer timeout, the bit will be clear. Then the
frequency will be decided by hardware default FS<4:0> or desired
frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ
(Reg0 - bit 0).
0 Reserved
0 Reserved
0 Reserved
3 IVAL<3>
1 Charge pump current selection
2 IVAL<2>
1
1 IVAL<1>
1
0 IVAL<0>
1
- 12 -










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