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PDF ( 数据手册 , 数据表 ) HD1-15530-9

零件编号 HD1-15530-9
描述 CMOS Manchester Encoder-Decoder
制造商 Intersil Corporation
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HD1-15530-9 数据手册, 描述, 功能
HD-15530
March 1997
CMOS Manchester Encoder-Decoder
Features
Description
• Support of MlL-STD-1553
• Data Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.25 MBit/s
• Sync Identification and Lock-In
• Clock Recovery
• Manchester II Encode, Decode
• Separate Encode and Decode
• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V
Ordering Information
PACKAGE
CERDIP
SMD#
CLCC
SMD#
PDIP
TEMP. RANGE
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
-55oC to +125oC
-40oC to +85oC
1.25 MEGABIT/s PKG. NO.
HD1-15530-9
F24.6
HD1-15530-8
7802901JA
HD4-15530-9
J28.A
HD4-15530-8
78029013A
HD3-15530-9
E24.6
The Intersil HD-15530 is a high performance CMOS device
intended to service the requirements of MlL-STD-1553 and
similar Manchester II encoded, time division multiplexed
serial data protocols. This LSI chip is divided into two
sections, an Encoder and a Decoder. These sections
operate completely independent of each other, except for the
Master Reset functions.
This circuit meets many of the requirements of MIL-STD-
1553. The Encoder produces the sync pulse and the parity
bit as well as the encoding of the data bits. The Decoder
recognizes the sync pulse and identifies it as well as decod-
ing the data bits and checking parity.
This integrated circuit is fully guaranteed to support the
1MHz data rate of MlL-STD-1553 over both temperature and
voltage. It interfaces with CMOS, TTL or N channel support
circuitry, and uses a standard 5V supply.
The HD-15530 can also be used in many party line digital
data communications applications, such as an environmen-
tal control system driven from a single twisted pair cable of
fiber optic cable throughout the building.
Pinouts
HD-15530 (CERDIP, PDIP)
TOP VIEW
VALID WORD 1
ENCODER
SHIFT CLK
2
TAKE DATA 3
SERIAL DATA OUT 4
DECODER CLK 5
BIPOLAR ZERO IN 6
BIPOLAR ONE IN 7
UNIPOLAR DATA IN 8
DECODER SHIFT CLK 9
COMMAND/
DATA SYNC
10
DECODER RESET 11
GND 12
24 VCC
23 ENCODER CLK
22 SEND CLK IN
21 SEND DATA
20 SYNC SELECT
19 ENCODER ENABLE
18 SERIAL DATA IN
17 BIPOLAR ONE OUT
16 OUTPUT INHIBIT
15
BIPOLAR
ZERO OUT
14 ÷ 6 OUT
13 MASTER RESET
HD-15530 (CLCC)
TOP VIEW
4 3 2 1 28 27 26
DECODER
CLK
5
25
SEND
DATA
NC 6
24 NC
NC 7
23 NC
BIPOLAR
ZERO IN
8
22
SYNC
SELECT
BIPOLAR
ONE IN
9
21
ENCODER
ENABLE
UNIPOLAR
DATA IN
10
20
SERIAL
DATA IN
DECODER
SHIFT CLK
11
19
BIPOLAR
ONE OUT
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
5-142
File Number 2960.1







HD1-15530-9 pdf, 数据表
HD-15530
AC Electrical Specifications VCC = 5V ±10%, TA = -40oC to +85oC (HD-15530-9)
TA = -55oC to +125oC (HD-15530-8)
PARAMETER
SYMBOL
(NOTE 2)
TEST CONDITIONS
LIMITS
MIN MAX
UNITS
ENCODER TIMING
Encoder Clock Frequency
FEC
VCC = 4.5V and 5.5V, CL = 50pF
-
15 MHz
Send Clock Frequency
FESC
VCC = 4.5V and 5.5V, CL = 50pF
-
2.5 MHz
Encoder Data Rate
FED
VCC = 4.5V and 5.5V, CL = 50pF
-
1.25 MHz
Master Reset Pulse Width
TMR
VCC = 4.5V and 5.5V, CL = 50pF
150
-
ns
Shift Clock Delay
TE1 VCC = 4.5V and 5.5V, CL = 50pF - 125 ns
Serial Data Setup
TE2 VCC = 4.5V and 5.5V, CL = 50pF
75
- ns
Serial Data Hold
TE3 VCC = 4.5V and 5.5V, CL = 50pF
75
- ns
Enable Setup
TE4 VCC = 4.5V and 5.5V, CL = 50pF
90
-
ns
Enable Pulse Width
TE5 VCC = 4.5V and 5.5V, CL = 50pF
100
-
ns
Sync Setup
TE6 VCC = 4.5V and 5.5V, CL = 50pF
55
-
ns
Sync Pulse Width
TE7 VCC = 4.5V and 5.5V, CL = 50pF
150
-
ns
Send Data Delay
TE8 VCC = 4.5V and 5.5V, CL = 50pF
0
50
ns
Bipolar Output Delay TE9 VCC = 4.5V and 5.5V, CL = 50pF - 130 ns
Enable Hold
TE10
VCC = 4.5V and 5.5V, CL = 50pF
10
-
ns
Sync Hold
TE11
VCC = 4.5V and 5.5V, CL = 50pF
95
-
ns
DECODER TIMING
Decoder Clock Frequency
Decoder Data Rate
Decoder Reset Pulse Width
Decoder Reset Setup Time
Decoder Reset Hold Time
Master Reset Pulse
Bipolar Data Pulse Width
FDC
FDD
TDR
TDRS
TDRH
TMR
TD1
VCC = 4.5V and 5.5V, CL = 50pF
VCC = 4.5V and 5.5V, CL = 50pF
VCC = 4.5V and 5.5V, CL = 50pF
VCC = 4.5V and 5.5V, CL = 50pF
VCC = 4.5V and 5.5V, CL = 50pF
VCC = 4.5V and 5.5V, CL = 50pF
VCC = 4.5V and 5.5V, CL = 50pF
-
-
150
75
10
150
TDC + 10
(Note 1)
15
1.25
-
-
-
-
-
MHz
MHz
ns
ns
ns
ns
ns
One Zero Overlap
TD3 VCC = 4.5V and 5.5V, CL = 50pF
-
TDC - 10
ns
(Note 1)
Sync Delay (ON)
TD6 VCC = 4.5V and 5.5V, CL = 50pF -20 110
ns
Take Data Delay (ON)
TD7 VCC = 4.5V and 5.5V, CL = 50pF
0
110 ns
Serial Data Out Delay
TD8 VCC = 4.5V and 5.5V, CL = 50pF
-
80 ns
Sync Delay (OFF)
TD9 VCC = 4.5V and 5.5V, CL = 50pF 0 110 ns
Take Data Delay (OFF)
TD10
VCC = 4.5V and 5.5V, CL = 50pF
0
110 ns
Valid Word Delay
TD11
VCC = 4.5V and 5.5V, CL = 50pF
0
110 ns
NOTES:
1. TDC = Decoder clock period = 1/FDC
2. AC Testing as follows: Input levels: VIH = 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing Reference levels: 1.5V;
Output load: CL = 50pF.
5-149














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HD1-15530-8CMOS Manchester Encoder-DecoderIntersil Corporation
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HD1-15530-9CMOS Manchester Encoder-DecoderIntersil Corporation
Intersil Corporation

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