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PDF ( 数据手册 , 数据表 ) NT5CB128M16FP-EK

零件编号 NT5CB128M16FP-EK
描述 Industrial and Automotive DDR3(L) 2Gb SDRAM
制造商 Nanya
LOGO Nanya LOGO 


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NT5CB128M16FP-EK 数据手册, 描述, 功能
DDR3(L) 2Gb SDRAM
NT5CB(C)256M8FN / NT5CB(C)128M16FP
Nanya Technology Corp.
NT5CB(C)256M8FN / NT5CB(C)128M16FP
Commercial, Industrial and Automotive DDR3(L) 2Gb SDRAM
Features
JEDEC DDR3 Compliant
- 8n Prefetch Architecture
- Differential Clock(CK/) and Data Strobe(DQS/)
- Double-data rate on DQs, DQS and DM
Data Integrity
- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
Power Saving Mode
- Partial Array Self Refresh (PASR)1
- Power Down Mode
Signal Integrity
- Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via
external ZQ pad (240 ohm ± 1%)
Signal Synchronization
- Write Leveling via MR settings 7
- Read Leveling via MPR
Interface and Power Supply
- SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V)
- SSTL_1354 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V)
Speed Grade (CL-TRCD-TRP) 2,3
- 2133 Mbps / 14-14-14
- 1866 Mbps / 12-12-12,13-13-13
- 1600 Mbps / 11-11-11
Options
Temperature Range (Tc) 5
- Commercial Grade = 0~95
- Industrial Grade (-I) = -40~95
- Automotive Grade 2 (-H) = -40~105
- Automotive Grade 3 (-A) = -40~95
Programmable Functions
CAS Latency (5/6/7/8/9/10/11/12/13/14)
CAS Write Latency (5/6/7/8/9/10)
Additive Latency (0/CL-1/CL-2)
Write Recovery Time (5/6/7/8/10/12/14/16)
Burst Type (Sequential/Interleaved)
Burst Length (BL8/BC4/BC4 or 8 on the fly)
Self RefreshTemperature Range(Normal/Extended)
Output Driver Impedance (34/40)
On-Die Termination of Rtt_Nom(20/30/40/60/120)
On-Die Termination of Rtt_WR(60/120)
Precharge Power Down (slow/fast)
Packages / Density Information
Lead-free RoHS compliance and Halogen-free
Density and Addressing
2Gb
(Org. / Package)
Length x Width Ball pitch
(mm)
(mm)
256Mbx8
78-ball
TFBGA
8.00 x 10.50
0.80
128Mbx16
96-ball
TFBGA
9.00 x 13.00
0.80
Organization
Bank Address
Auto precharge
BL switch on the fly
Row Address
Column Address
Page Size
tREFI(us) 5
tRFC(ns) 6
256Mb x 8
128Mb x 16
BA0 BA2
BA0 BA2
A10 / AP
A12 / 
A10 / AP
A12 / 
A0 A14
A0 A9
A0 A13
A0 A9
1KB 2KB
Tc<=85:7.8, Tc>85:3.9
160ns
NOTE 1
NOTE 2
NOTE 3
NOTE 4
NOTE 5
NOTE 6
NOTE 7
Default state of PASR is disabed. This is enabled by using an electrical fuse. Please contact with NTC for the demand.
The timing specification of high speed bin is backward compatible with low speed bin.
Please refer to ordering information for the deailts (DDR3, DDR3L, DDR3L RS).
SSTL_135 compatible to SSTL_15. That means 1.35V DDR3L are backward compatible to 1.5V DDR3 parts. 1.35V DDR3L-RS parts are exceptional
and unallowable to be compatible to 1.35V DDR3L and 1.5V DDR3 parts.
If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9us interval refresh rate. Extended SRT or ASR must be enabled.
Violating tRFC specification will induce malfunction.
Only Support prime DQs feedback for each byte lane.
Version 1.6
04/2014
1 Nanya Technology Cooperation ©
NTC has the rights to change any specifications or product without notification.
All Rights Reserved.







NT5CB128M16FP-EK pdf, 数据表
DDR3(L) 2Gb SDRAM
NT5CB(C)256M8FN / NT5CB(C)128M16FP
Ball Descriptions
Symbol
Type
 Input
CKE
Input

RA, A, WE
For x8,
DM
For x16,
DMU, DML
Input
Input
Input
Function
Clock: CK and  are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of .
Clock Enable: CKE high activates, and CKE low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE low provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is
synchronous for power down entry and exit and for Self-Refresh entry. CKE is asynchronous for
Self-Refresh exit. After VREF has become stable during the power on and initialization sequence,
it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and
exit, VREF must maintain to this input. CKE must be maintained high throughout read and write
accesses. Input buffers, excluding CK, , ODT and CKE are disabled during Power Down. Input
buffers, excluding CKE, are disabled during Self-Refresh.
Chip Select: All commands are masked when  is registered high.  provides for external
rank selection on systems with multiple memory ranks.  is considered part of the command
code.
Command Inputs: RA, A and WE (along with ) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH coincident with that input data during a Write access. DM is sampled on both
edges of DQS. For x8 device, the function of DM or TDQS/T is enabled by Mode Register
A11 setting in MR1.
BA0 - BA2
A10 / AP
For x8,
A0 A14
For x16,
A0 A13
A12/
ODT
Input
Input
Input
Input
Input
Bank Address Inputs: BA0, BA1, and BA2 define to which bank an Active, Read, Write or
Precharge command is being applied. Bank address also determines which mode register is to be
accessed during a MRS cycle.
Auto-Precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation. (HIGH:
Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge command to
determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only
one bank is to be precharged, the bank is selected by bank addresses.
Address Inputs: Provide the row address for Activate commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
(A10/AP and A12/ have additional function as below.) The address inputs also provide the
op-code during Mode Register Set commands.
Burst Chop: A12/is sampled during Read and Write commands to determine if burst chop
(on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is applied to each DQ, DQS, and DM/TDQS, NU/T
(when TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT
pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT.
Version 1.6
04/2014
8 Nanya Technology Cooperation ©
All Rights Reserved.







NT5CB128M16FP-EK equivalent, schematic
DDR3(L) 2Gb SDRAM
NT5CB(C)256M8FN / NT5CB(C)128M16FP
tMOD Timing
CK
CK
CMD
ADDR
MRS
VAL
NOP
NOP
tMOD
NOP
CKE
Old Setting
Updating Setting
NOP
Non
MRS
VAL
VAL
New Setting
Programming the Mode Registers (Cont’d)
The mode register contents can be changed using the same command and timing requirements during normal operation as
long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed
and CKE is high prior to writing into the mode register. The mode registers are divided into various fields depending on the
functionality and/or modes.
Mode Register MR0
The mode-register MR0 stores data for controlling various operating modes of DDR3 (L) SDRAM. It controls burst length,
read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include
various vendor specific options to make DDR3(L) SDRAM useful for various applications. The mode register is written by
asserting low on , RA, A, WE, BA0, BA1, and BA2, while controlling the states of address pins according to the
following figure.
Version 1.6
04/2014
16 Nanya Technology Cooperation ©
All Rights Reserved.










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