DataSheet8.cn


PDF ( 数据手册 , 数据表 ) G2216-208-041PFB2

零件编号 G2216-208-041PFB2
描述 Transceiver
制造商 GlobespanVirata
LOGO GlobespanVirata LOGO 


1 Page

No Preview Available !

G2216-208-041PFB2 数据手册, 描述, 功能
June 25, 2002, Issue 2
Part Numbers
G2216-208-041PF B2 (SDSL 2B1Q)
G2214-208-041DF B2 (SDSL CAP)
G2237-208-041PT B2 (SHDSL/HDSL2)
G2237-208-041PT C1 (SHDSL/HDSL2)
XDSL2TM SDSL, HDSL2, or SHDSL - ILD2
Dual-Channel, Low Power, Programmable
Transceiver with Integrated Framer and Line Drivers
Data Sheet
Overview
The GlobespanVirata® XDSL2™ Digital Subscriber Line
(DSL) chip sets provide low power, high density solutions for
2-wire DSL equipment. These chip sets are fully
programmable and field upgradeable eliminating the risk of
product obsolescence and accelerating the time-to-market for
new network services. The GlobespanVirata® XDSL2™ DSL
chip sets are fully interoperable with multi-vendor DSL chip
set solutions. This interoperability enables dynamic
interworking of multiple vendor DSL solutions with the
capability to interoperate with products that conform to ANSI
and ETSI DSL standards.
GlobespanVirata’s unique hardware platform supports
multiple dual-channel applications including SDSL, HDSL2,
and SHDSL, using population options for optimization.
The XDSL2 DSL chip sets incorporate two DSL bit pumps
plus framing into a three-chip solution comprised of a dual-
channel digital signal processor (DSP) with built-in framer and
two Analog Front Ends each with an Integrated Line Driver
(ILD2).
The XDSL2 chip sets interface directly with off-the-shelf T1/
E1 transceivers and Nx64 multiplexing, eliminating the need
for a separate DSL framer to combine and format the two DSL
channels into a standard interface. GlobespanVirata’s DSL
XDSL2 chip sets deliver two channels of full duplex
transmission up to 2320 kb/s, depending on the application.
The high density XDSL2 dual-channel DSL chip sets are ideal
for CO applications, while single-channel versions with
integrated framer are also available for CPE applications.
Features
Dual-channel DSP with framer that fully integrates
2 separate DSL chips into a single device
Two AFEs, each with an integrated differential line driver
2B1Q, CAP, or PAM line codes
Supports dual-channel symmetric data rates of 144 kb/s
to 2320 kb/s (depending on the application)
Supports IDSL with optional data interface rates of
64 kb/s, 128 kb/s, and 144 kb/s
Offers physical layer interoperability with competitive solu-
tions
Glueless interface to popular microprocessors
Transmission compliant with ETSI TS 101 135, ITU-T
G.991.1, and ANSI TR-28 for single pair 2B1Q and CAP,
ANSI T1.418 for HDSL2 and ITU-T G.991.2 for SHDSL
Reference design compatible with Bellcore GR-1089, IEC
60950, UL 1950, ITU-T K.20 and K.21
Built-in framer provides easy access to EOC and indicator
bits (framing can be bypassed completely for 2-channel
independent operation)
Interfaces directly with off-the-shelf single-channel T1/E1
transceivers
ATM UTOPIA Level 1 and 2 interface
A single oscillator and hybrid topology supports all speeds
+3.3V and +5V power supplies
Customer Interface
TDATA (A/B)
TClock (A/B)
Frame Pulse (A/B)
RDATA (A/B)
Rclock (A/B)
Frame Pulse (A/B)
Dual
Channel
DSP
w/Framer
µ Processor Interface
ILD2
ILD2
Figure 1. Block Diagram of XDSL2™ DSP with Two Single-Channel ILD2s
GlobespanVirata, Inc. — Proprietary
Use pursuant to Company Instructions
DO-009643-DS, Issue 2







G2216-208-041PFB2 pdf, 数据表
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
June 25, 2002
Performance
GlobespanVirata has rigorously tested the performance of the DSL chip sets, with the results detailed in Table 8,
Table 9, Table 10 and Table 11.
Table 8. SDSL 2B1Q Performance Specifications
(Reach in kft and km)
Line Rate
(kb/s)
No Noise
24 AWG
26 AWG
kft km kft km
144
272
400
528
784
1040
1168
1552
2064
2320
25.4 7.7 21.0 6.4
23.6 7.2 19.5 5.9
22.4 6.8 17.3 5.2
21.3 6.5 16.1 4.9
19.1 5.8 15.2 4.6
17.6 5.4 14.4 4.4
15.9 4.8 13.8 4.2
13.3 4.1 12.7 3.9
11.8 3.6
11.1 3.4
11.3
3.4
10.9
3.3
Table 9. SDSL CAP Performance Specifications
(Reach in kft and km)
Line Rate
(kb/s)
No Noise
24 AWG
26 AWG
kft km kft km
144
272
400
528
784
1040
1552
2064
2320
30.4 9.2 21.4 6.5
30.3 9.2 20.3 6.1
28.7 8.7 18.8 5.7
26.2 7.9 17.0 5.3
23.1 7.0 15.8 4.8
22.4 6.8 15.5 4.7
19.4 5.9 13.9 4.2
17.2 5.2 12.2 3.7
15.8 4.8 11.7 3.5
Table 10. HDSL2 Performance Specifications
(Reach in kft and km)
Line Rate
(kb/s)
No Noise
24 AWG
26 AWG
kft km kft km
T1
(1.552 kb/s)
18.0 5.5 13.5 4.1
Table 11. SHDSL Performance Specifications
(Reach in kft and km)
Line Rate
(kb/s)
No Noise
26 AWG
kft km
144
200
392
520
776
1032
1168
1544
2056
2312
26.0
21.4
19.9
18.7
17.5
16.6
15.8
14.0
13.0
12.5
7.9
6.5
6.0
5.7
5.3
5.1
4.8
4.2
3.9
3.8
NOTE:
All Nx64 payload rates are supported (where N= 3
through 36). The line rates listed in Table 11 are a
few typical data points.
GlobespanVirata, Inc. — Proprietary
8
Use pursuant to Company Instructions
DO-009643-DS, Issue 2







G2216-208-041PFB2 equivalent, schematic
XDSL2TM SDSL, HDSL2, and SHDSL - ILD2 Data Sheet
June 25, 2002
Boundary-Scan Testing
Four pins are provided for compliance to IEEE Standard 1149.1 (JTAG) for boundary scan testing. These DSP pins
are used to control and communicate with the boundary-scan logic. JTAG support is available only in Revision “C1”
of the DSP/Framer. Table 13 provides a list of the four JTAG pins:
Table 13. Boundary-Scan Pins
144-Pin
DSP/Framer Revision “C1”
Pin #
9
18
29
85
JTAG Description
TMS - Test Mode Select
TDI - Test Data Input
TDO - Test Data Output
TCK - Test Clock
Table 14. Dual-Channel DSP/Framer Electrical Characteristics
Parameters
Min Nom Max
Absolute Maximum Ratings
Power Supply Voltage, VDD
Power Supply Voltage, AVDD
Input Voltage
Storage Temperature
Junction Temperature
Recommended Operating Conditions
Power Supply Voltage, VDD
Power Supply Voltage, AVDD
Input Voltage
Operating Temperature
Digital Specifications
I/O Levels
Digital Inputs
GND – 0.3
–40
3.6
3.6
5.5
125
125
3.13
2.75
GND – 0.3
–40
3.3
3.3
3.3
25
3.47
3.47
5.5
85
TTL and/or CMOS compatible
Input Low Voltage, VIL
–0.3
0
Input High Voltage, VIH
Digital Outputs
2.0 3.3
Output Low Voltage, VOL
Output High Voltage, VOH
for Rev. B2 of the DSP
—0
2.4 3.3
Output High Voltage, VOH
for Rev. C1 of the DSP
2.4 3.3
DC Specifications
Input Leakage Current, ILI
10 —
High-Z Leakage Current, ILO
Input Capacitance, CIN (fc = 1 MHz)
I/O Capacitance, CIO (fc = 1 MHz)
10
6
10
Note: All of the following pins are 5V tolerant:
All Input (I) signal pins except XTLI
All Input/Output (I/O) signal pins
No Output (O) signal pins except INTA, INTB, and POP2A
0.8
5.25
0.4
Unit
V
V
V
°C
°C
V
V
V
°C
Test Conditions/Comments
V
For all inputs except XTLI. For XTLI, the maximum VIL
is VDD/2.
V
V Current sink, IOL, 3.5 mA
V Current load, IOH, 6 mA for all pins
V
Current load, IOH, 6 mA for all non-UTOPIA pins
Current load, IOH, 10 mA for all UTOPIA pins
µA Input voltage, VI, between 0 volts and VDD
µA Output voltage, VO, between 0 volts and VDD
pF
pF
GlobespanVirata, Inc. — Proprietary
16
Use pursuant to Company Instructions
DO-009643-DS, Issue 2










页数 30 页
下载[ G2216-208-041PFB2.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
G2216-208-041PFB2TransceiverGlobespanVirata
GlobespanVirata

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap