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PDF ( 数据手册 , 数据表 ) AT45DB321D

零件编号 AT45DB321D
描述 2.5V or 2.7V DataFlash
制造商 Adesto
LOGO Adesto LOGO 


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AT45DB321D 数据手册, 描述, 功能
AT45DB321D
32Mb, 2.5V or 2.7V
DataFlash
DATASHEET
(NOT RECOMMENDED FOR NEW DESIGNS. USE AT45DB321E.)
Features
Single 2.5V - 3.6V or 2.7V - 3.6V supply
RapidSserial interface: 66MHz maximum clock frequency
SPI compatible modes 0 and 3
User configurable page size
512 bytes per page
528 bytes per page
Page size can be factory preconfigured for 512 bytes
Page program operation
Intelligent programming operation
8,192 pages (512/528 bytes/page) main memory
Flexible erase options
Page erase (512 bytes)
Block erase (4KB)
Sector erase (64KB)
Chip erase (32Mb)
Two SRAM data buffers (512/528 bytes)
Allows receiving data while reprogramming the flash array
Continuous read capability through entire array
Ideal for code shadowing applications
Low power dissipation
7mA active read current ,typical
25μA standby current, typical
15μA deep power down, typical
Hardware and software data protection features
Individual sector
Sector lockdown for secure code and data storage
Individual sector
Security: 128-byte security register
64-byte user programmable space
Unique 64-byte device identifier
JEDEC standard manufacturer and device ID read
100,000 program/erase cycles per page, minimum
Data retention: 20 years
Industrial temperature range
Green (Pb/halide-free/RoHS compliant) packaging options
3597T–DFLASH–11/2013







AT45DB321D pdf, 数据表
5.5 Block Erase
A block of eight pages can be erased at one time. This command is useful when large amounts of data have to be written into
the device. This will avoid using multiple page erase commands. To perform a block erase for the standard DataFlash page size
(528-bytes), an opcode of 50H must be loaded into the device, followed by three address bytes comprised of 1 don’t care bit,
10 page address bits (PA12-PA3), and 13 don’t care bits. The 10 page address bits are used to specify which block of eight
pages is to be erased. To perform a block erase for the binary page size (512 bytes), the 50H opcode must be loaded into the
device, followed by three address bytes consisting of 2 don’t care bits, 10 page address bits (A21 - A12), and 12 don’t care bits.
The 10 page address bits are used to specify which block of eight pages is to be erased. When a low-to-high transition occurs
on the CS pin, the part will erase the selected block of eight pages. The erase operation is internally self-timed, and should take
place in a maximum time of tBE. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy.
Table 5-1. Block Erase Addressing
PA12/
A21
PA11/ PA10/
A20 A19
PA9/
A18
PA8/
A17
PA7/
A16
PA6/
A15
PA5/
A14
PA4/
A13
PA3/
A12
PA2/
A11
PA1/
A10
PA0/
A9
0 0 0 0 0 0 0 0 0 0XXX
0 0 0 0 0 0 0 0 0 1XXX
0 0 0 0 0 0 0 0 1 0XXX
0 0 0 0 0 0 0 0 1 1XXX
●●●●●●●●●●●●●
●●●●●●●●●●●●●
●●●●●●●●●●●●●
1 1 1 1 1 1 1 1 0 0XXX
1 1 1 1 1 1 1 1 0 1XXX
1 1 1 1 1 1 1 1 1 0XXX
1 1 1 1 1 1 1 1 1 1XXX
Block
0
1
2
3
1020
1021
1022
1023
5.6 Sector Erase
The sector erase command can be used to individually erase any sector in the main memory. There are 64 sectors, and only
one sector can be erased at a time. To perform a sector 0a or sector 0b erase for the standard DataFlash page size (528 bytes),
an opcode of 7CH must be loaded into the device, followed by three address bytes comprised of 1 don’t care bit, 10 page
address bits (PA12 - PA3), and 13 don’t care bits. To perform a sector 1-63 erase, the 7CH opcode must be loaded into the
device, followed by three address bytes comprised of 1 don’t care bit, 6 page address bits (PA12 - PA7), and 17 don’t care bits.
To perform a sector 0a or sector 0b erase for the binary page size (512 bytes), an opcode of 7CH must be loaded into the
device, followed by three address bytes comprised of 2 don’t care bits, 10 page address bits (A21 - A12), and 12 don’t care bits.
To perform a sector 1-63 erase, the 7CH opcode must be loaded into the device, followed by three address bytes comprised of
2 don’t care bits, 6 page address bits (A21 - A16), and 16 don’t care bits. The page address bits are used to specify any valid
address location within the sector to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the
selected sector. The erase operation is internally self-timed, and should take place in a maximum time of tSE. During this time,
the status register and the RDY/BUSY pin will indicate that the part is busy.
AT45DB321D [DATASHEET]
3597T–DFLASH–11/2013
8







AT45DB321D equivalent, schematic
8.1.2
Reading the Sector Lockdown Register
The sector lockdown register can be read to determine which sectors in the memory array are permanently locked down. To
read the sector lockdown register, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of 35H and
three dummy bytes must be clocked into the device via the SI pin. After the last bit of the opcode and dummy bytes has been
clocked in, the data for the content of the sector lockdown register will be clocked out on the SO pin. The first byte corresponds
to sector 0 (0a, 0b) the second byte corresponds to sector 1, and the last byte (byte 16) corresponds to sector 15. After the last
byte of the sector lockdown register has been read, additional pulses on the SCK pin will simply result in undefined data being
output on the SO pin.
Deasserting the CS pin will terminate the read sector lockdown register operation and put the SO pin into a high-impedance
state.
Table 8-4 details the values read from the sector lockdown register.
Table 8-4. Sector Lockdown Register
Command
Read sector lockdown register
Byte 1
35H
Byte 2
xxH
Byte 3
xxH
Byte 4
xxH
Note:
xx = Dummy byte.
Figure 8-2. Read Sector Lockdown Register
CS
SI
Opcode
X
X
X
SO
Each transition
represents 8 bits
Data byte
n
Data byte
n+1
Data byte
n + 63
8.2 Security Register
The device contains a specialized security register that can be used for purposes such as unique device serialization or locked
key storage. The register is comprised of a total of 128 bytes that are divided into two portions. The first 64 bytes (byte locations
0 through 63) of the security register are allocated as a one-time user programmable space. Once these 64 bytes have been
programmed, they cannot be reprogrammed. The remaining 64 bytes of the register (byte locations 64 through 127) are factory
programmed by Adesto, and contain a unique value for each device. The factory programmed data are fixed and cannot be
changed.
Table 8-5. Security Register
Data type
Security Register Byte Number
0 1 · · · 62 63 64 65 · · · 126 127
One-time user programmable
Adesto factory programmed
AT45DB321D [DATASHEET]
3597T–DFLASH–11/2013
16










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