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PDF ( 数据手册 , 数据表 ) AT45DB161E-SSHF-T

零件编号 AT45DB161E-SSHF-T
描述 2.3V or 2.5V Minimum SPI Serial Flash Memory
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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AT45DB161E-SSHF-T 数据手册, 描述, 功能
Atmel AT45DB161E
16-Mbits DataFlash (with Extra 512-Kbits), 2.3V or 2.5V Minimum
SPI Serial Flash Memory
Features
PRELIMINARY DATASHEET
Single 2.3V - 3.6V or 2.5V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI modes 0 and 3
Supports Atmel® RapidSoperation
Continuous Read capability through entire array
Up to 85MHz
Low-power Read option up to 10MHz
Clock-to-output time (tV) of 6ns maximum
User configurable page size
512 bytes per page
528 bytes per page (default)
Page size can be factory pre-configured for 512 bytes
Two fully independent SRAM data buffers (512/528 bytes)
Allows receiving data while reprogramming the Main Memory Array
Flexible programming options
Byte/Page program (1 to 512/528 bytes) directly into main memory
Buffer Write
Buffer to Main Memory Page Program
Flexible Erase options
Page Erase (512/528 bytes)
Block Erase (4KB)
Sector Erase (128KB)
Chip Erase (16-Mbits)
Program and Erase Suspend/Resume
Advanced hardware and software data protection features
Individual sector protection
Individual sector lockdown to make any sector permanently read-only
128-byte, One-Time Programmable (OTP) Security Register
64 bytes factory programmed with a unique identifier
64 bytes user programmable
Software controlled reset
JEDEC Standard Manufacturer and Device ID Read
Low-power dissipation
500nA Ultra-Deep Power-Down current (typical)
3μA Deep Power-Down current (typical)
25μA Standby current (typical)
11mA Active Read current (typical)
Endurance: 100,000 program/erase cycles per page minimum
Data retention: 20 years
Complies with full industrial temperature range
Green (Pb/Halide-free/RoHS compliant) packaging options
8-lead SOIC (0.150" wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
9-ball Chip-scale BGA (5 x 5 x 1.2mm)
8782A–DFLASH–3/12







AT45DB161E-SSHF-T pdf, 数据表
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
5.3 Continuous Array Read (High Frequency Mode: 0Bh Opcode)
This command can be used with the serial interface to read the Main Memory Array sequentially in High-Speed mode for
any clock frequency up to the maximum specified by fCAR1. To perform a Continuous Read Array with the standard
DataFlash page size (528 bytes), the CS must first be asserted then an opcode 0Bh must be clocked into the device
followed by three address bytes and one dummy byte. The first 12 bits (PA11 - PA0) of the 22-bit address sequence
specify which page of the Main Memory Array to read and the last 10 bits (BA9 - BA0) of the 22-bit address sequence
specify the starting byte address within the page. To perform a Continuous Read with the binary page size (512 bytes),
the opcode 0Bh must be clocked into the device followed by three address bytes (A20 - A0) and one dummy byte.
Following the dummy byte, additional clock pulses on the SCK pin will result in data being output on the SO pin.
The CS pin must remain low during the loading of the opcode, the address bytes, the dummy byte, and the reading of
data. When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue
reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the Main Memory Array has been read,
the device will continue reading back at the beginning of the first page of memory. As with crossing over page
boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR1 specification. The Continuous Array
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
5.4 Continuous Array Read (Low Frequency Mode: 03h Opcode)
This command can be used with the serial interface to read the Main Memory Array sequentially without dummy bytes up
to maximum frequencies specified by fCAR2. To perform a Continuous Read Array with the standard DataFlash page size
(528 bytes), the CS must first be asserted then an opcode 03h must be clocked into the device followed by three address
bytes. The first 12 bits (PA11 - PA0) of the 22 bit address sequence specify which page of the Main Memory Array to
read and the last 10 bits (BA9 - BA0) of the 22 bit address sequence specify the starting byte address within the page. To
perform a Continuous Read with the binary page size (512 bytes), the opcode 03h must be clocked into the device
followed by three address bytes (A20 - A0). Following the address bytes, additional clock pulses on the SCK pin will
result in data being output on the SO pin.
The CS pin must remain low during the loading of the opcode, the address bytes, and the reading of data. When the end
of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the
beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of
one page to the beginning of the next page). When the last bit in the Main Memory Array has been read, the device will
continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays
will be incurred when wrapping around from the end of the array to the beginning of the array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output pin (SO). The maximum
SCK frequency allowable for the Continuous Array Read is defined by the fCAR2 specification. The Continuous Array
Read bypasses both data buffers and leaves the contents of the buffers unchanged.
5.5 Continuous Array Read (Low Power Mode: 01h Opcode)
This command is ideal for applications that want to minimize power consumption and do not need to read the memory
array at high frequencies. The command allows reading the main memory array sequentially without dummy bytes up to
maximum frequencies specified by fCAR3. To perform a Continuous Read Array with the standard DataFlash page size
(528 bytes), the CS must first be asserted then an opcode 01h must be clocked into the device followed by three address
bytes. The first 12 bits (PA11 - PA0) of the 22 bit address sequence specify which page of the Main Memory Array to
read and the last 10 bits (BA9 - BA0) of the 22 bit address sequence specify the starting byte address within the page. To
perform a Continuous Read with the binary page size (512 bytes), the opcode 01h must be clocked into the device
Atmel AT45DB161E [PRELIMINARY DATASHEET]
8782A–DFLASH–3/12
8







AT45DB161E-SSHF-T equivalent, schematic
Table 6-4. Operations Allowed and Not Allowed During Suspend
Command
Read Commands
Read Array (All Opcodes)
Read Buffer 1 (All Opcodes)
Read Buffer 2 (All Opcodes)
Program and Erase Commands
Buffer 1 Write
Buffer 2 Write
Buffer 1 to Memory Program w/ Erase
Buffer 2 to Memory Program w/ Erase
Buffer 1 to Memory Program w/o Erase
Buffer 2 to Memory Program w/o Erase
Memory Program through Buffer 1 w/ Erase
Memory Program through Buffer 2 w/ Erase
Memory Program through Buffer 1 w/o Erase
Auto Page Rewrite
Page Erase
Block Erase
Sector Erase
Chip Erase
Protection and Security Commands
Enable Sector Protection
Disable Sector Protection
Erase Sector Protection Register
Program Sector Protection Register
Read Sector Protection Register
Sector Lockdown
Read Sector Lockdown
Freeze Sector Lockdown State
Program Security Register
Read Security Register
Additional Commands
Main Memory to Buffer 1 Transfer
Main Memory to Buffer 2 Transfer
Main Memory to Buffer 1 Compare
Main Memory to Buffer 2 Compare
Enter Deep Power-Down
Resume from Deep Power-Down
Enter Ultra-Deep Power-Down mode
Read Configuration Register
Read Status Register
Read Manufacturer and Device ID
Reset (via Hardware or Software)
Operation During
Program Suspend in
Buffer 1 (PS1)
Operation During
Program Suspend in
Buffer 2 (PS2)
Operation During
Erase Suspend (ES)
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Not Allowed
Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Allowed
Allowed
Not Allowed
Not Allowed
Allowed
Allowed
Not Allowed
Not Allowed
Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Allowed
Not Allowed
Allowed
Not Allowed
Not Allowed
Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Allowed
Not Allowed
Allowed
Not Allowed
Not Allowed
Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Allowed
Not Allowed
Allowed
Not Allowed
Not Allowed
Allowed
Not Allowed
Allowed
Allowed
Allowed
Not Allowed
Not Allowed
Not Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Not Allowed
Allowed
Allowed
Not Allowed
Not Allowed
Not Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Not Allowed
Not Allowed
Not Allowed
Allowed
Allowed
Allowed
Allowed
Atmel AT45DB161E [PRELIMINARY DATASHEET]
8782A–DFLASH–3/12
16










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