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PDF ( 数据手册 , 数据表 ) AT45DB041D-SSU

零件编号 AT45DB041D-SSU
描述 4-megabit 2.5-volt or 2.7-volt DataFlash
制造商 Adesto
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AT45DB041D-SSU 数据手册, 描述, 功能
Features
Single 2.5V or 2.7V to 3.6V Supply
RapidSTM Serial Interface: 66MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
User Configurable Page Size
– 256-Bytes per Page
– 264-Bytes per Page
– Page Size Can Be Factory Pre-configured for 256-Bytes
Page Program Operation
– Intelligent Programming Operation
– 2,048 Pages (256-/264-Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (256-Bytes)
– Block Erase (2-Kbytes)
– Sector Erase (64-Kbytes)
– Chip Erase (4Mbits)
Two SRAM Data Buffers (256-, 264-Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 7mA Active Read Current Typical
– 25μA Standby Current Typical
– 15μA Deep Power-down Typical
Hardware and Software Data Protection Features
– Individual Sector
Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
4-megabit
2.5-volt or
2.7-volt
DataFlash®
AT45DB041D
(Not recommended for
new designs. Use
AT45DB041E.)
1. Description
The AT45DB041D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a
wide variety of digital voice-, image-, program code- and data-storage applications.
The AT45DB041D supports RapidS serial interface for applications requiring very
high speed operations. RapidS serial interface is SPI compatible for frequencies up to
66MHz. Its 4,325,376-bits of memory are organized as 2,048 pages of 256-bytes or
264-bytes each. In addition to the main memory, the AT45DB041D also contains two
SRAM buffers of 256-/264-bytes each. The buffers allow the receiving of data while a
page in the main Memory is being reprogrammed, as well as writing a continuous data
stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-con-
tained three step read-modify-write operation. Unlike conventional Flash memories
that are accessed randomly with multiple address lines and a parallel interface, the
DataFlash uses a RapidS serial interface to sequentially access its data. The simple
sequential access dramatically
3595T–DFLASH–8/2013







AT45DB041D-SSU pdf, 数据表
7.2 Buffer to Main Memory Page Program with Built-in Erase
Data written into either buffer 1 or buffer 2 can be programmed into the main memory. A 1-byte
opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the device. For the DataFlash
standard page size (264-bytes), the opcode must be followed by three address bytes consist of
four don’t care bits, 11 page address bits (PA10 - PA0) that specify the page in the main memory
to be written and nine don’t care bits. To perform a buffer to main memory page program with
built-in erase for the binary page size (256-bytes), the opcode 83H for buffer 1 or 86H for buffer
2, must be clocked into the device followed by three address bytes consisting of five don’t care
bits 11 page address bits (A18 - A8) that specify the page in the main memory to be written and
eight don’t care bits. When a low-to-high transition occurs on the CS pin, the part will first erase
the selected page in main memory (the erased state is a logic 1) and then program the data
stored in the buffer into the specified page in main memory. Both the erase and the program-
ming of the page are internally self-timed and should take place in a maximum time of tEP.
During this time, the status register will indicate that the part is busy.
7.3 Buffer to Main Memory Page Program without Built-in Erase
A previously-erased page within main memory can be programmed with the contents of either
buffer 1 or buffer 2. A 1-byte opcode, 88H for buffer 1 or 89H for buffer 2, must be clocked into
the device. For the DataFlash standard page size (264-bytes), the opcode must be followed by
three address bytes consist of four don’t care bits, 11 page address bits (PA10 - PA0) that spec-
ify the page in the main memory to be written and nine don’t care bits. To perform a buffer to
main memory page program without built-in erase for the binary page size (256-bytes), the
opcode 88H for buffer 1 or 89H for buffer 2, must be clocked into the device followed by three
address bytes consisting of five don’t care bits, 11 page address bits (A18 - A8) that specify the
page in the main memory to be written and eight don’t care bits. When a low-to-high transition
occurs on the CS pin, the part will program the data stored in the buffer into the specified page in
the main memory. It is necessary that the page in main memory that is being programmed has
been previously erased using one of the erase commands (Page Erase or Block Erase). The
programming of the page is internally self-timed and should take place in a maximum time of tP.
During this time, the status register will indicate that the part is busy.
7.4 Page Erase
The Page Erase command can be used to individually erase any page in the main memory array
allowing the Buffer to Main Memory Page Program to be utilized at a later time. To perform a
page erase in the DataFlash standard page size (264-bytes), an opcode of 81H must be loaded
into the device, followed by three address bytes comprised of four don’t care bits, 11 page
address bits (PA10 - PA0) that specify the page in the main memory to be erased and nine don’t
care bits. To perform a page erase in the binary page size (256-bytes), the opcode 81H must be
loaded into the device, followed by three address bytes consist of five don’t care bits, 11 page
address bits (A18 - A8) that specify the page in the main memory to be erased and eight don’t
care bits. When a low-to-high transition occurs on the CS pin, the part will erase the selected
page (the erased state is a logical 1). The erase operation is internally self-timed and should
take place in a maximum time of tPE. During this time, the status register will indicate that the
part is busy.
8 AT45DB041D
3595T–DFLASH–8/2013







AT45DB041D-SSU equivalent, schematic
Table 9-5. Program Sector Protection Register Command
Command
Program Sector Protection Register
Byte 1
3DH
Byte 2
2AH
Figure 9-3. Program Sector Protection Register
CS
Byte 3
7FH
Byte 4
FCH
SI
Opcode
Byte 1
Each transition
represents 8 bits
Opcode
Byte 2
Opcode
Byte 3
Opcode
Byte 4
Data Byte
n
Data Byte
n+1
Data Byte
n+7
9.1.3
Read Sector Protection Register Command
To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has
been asserted, an opcode of 32H and three dummy bytes must be clocked in via the SI pin. After
the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on
the SCK pins will result in data for the content of the Sector Protection Register being output on
the SO pin. The first byte corresponds to sector 0 (0a, 0b), the second byte corresponds to sec-
tor 1 and the last byte (byte 8) corresponds to sector seven. Once the last byte of the Sector
Protection Register has been clocked out, any additional clock pulses will result in undefined
data being output on the SO pin. The CS must be deasserted to terminate the Read Sector Pro-
tection Register operation and put the output into a high-impedance state.
Table 9-6. Read Sector Protection Register Command
Command
Read Sector Protection Register
Note: xx = Dummy Byte
Byte 1
32H
Byte 2
xxH
Byte 3
xxH
Byte 4
xxH
Figure 9-4. Read Sector Protection Register
CS
9.1.4
SI
Opcode
X
X
X
SO
Each transition
represents 8 bits
Data Byte
n
Data Byte
n+1
Data Byte
n+7
Various Aspects About the Sector Protection Register
The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Users are
encouraged to carefully evaluate the number of times the Sector Protection Register will be
modified during the course of the applications’ life cycle. If the application requires that the Sec-
tor Protection Register be modified more than the specified limit of 10,000 cycles because the
application needs to temporarily unprotect individual sectors (sector protection remains enabled
while the Sector Protection Register is reprogrammed), then the application will need to limit this
practice. Instead, a combination of temporarily unprotecting individual sectors along with dis-
abling sector protection completely will need to be implemented by the application to ensure that
the limit of 10,000 cycles is not exceeded.
16 AT45DB041D
3595T–DFLASH–8/2013










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