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PDF ( 数据手册 , 数据表 ) AT45DB011D-MH-SL954

零件编号 AT45DB011D-MH-SL954
描述 1-megabit 2.7-volt Minimum DataFlash
制造商 Adesto
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AT45DB011D-MH-SL954 数据手册, 描述, 功能
Features
Single 2.7V to 3.6V Supply
RapidSSerial Interface: 66MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
User Configurable Page Size
– 256-Bytes per Page
– 264-Bytes per Page
– Page Size Can Be Factory Pre-configured for 256-Bytes
Page Program Operation
– Intelligent Programming Operation
– 512-Pages (256-/264-Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (256-Bytes)
– Block Erase (2-Kbytes)
– Sector Erase (32-Kbytes)
– Chip Erase (1Mbits)
One SRAM Data Buffer (256-/264-Bytes)
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 7mA Active Read Current Typical
– 25µA Standby Current Typical
– 15µA Deep Power-down Typical
Hardware and Software Data Protection Features
– Individual Sector
Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
1-megabit
2.7-volt
Minimum
DataFlash®
AT45DB011D
1. Description
The Adesto® AT45DB011D is a 2.7V, serial-interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
The AT45DB011D supports RapidS serial interface for applications requiring very
high speed operations. RapidS serial interface is SPI compatible for frequencies up to
66MHz. Its 1,081,344-bits of memory are organized as 512 pages of 256-bytes or
264-bytes each. In addition to the main memory, the AT45DB011D also contains one
SRAM buffer of 256-/264-bytes. EEPROM emulation (bit or byte alterability) is easily
handled with a self-contained three step read-modify-write operation. Unlike conven-
tional Flash memories that are accessed randomly with multiple address lines and a
parallel interface, the Adesto DataFlash® uses a RapidS serial interface to sequen-
tially access its data. The simple sequential access dramatically reduces active pin
count, facilitates hardware layout, increases system reliability, minimizes switching
noise, and reduces package size.
3639K–DFLASH–6/2014







AT45DB011D-MH-SL954 pdf, 数据表
bytes), the opcode 83H must be clocked into the device followed by three address bytes consist-
ing of seven don’t care bits, nine page address bits (A16 - A8) that specify the page in the main
memory to be written and eight don’t care bits. When a low-to-high transition occurs on the CS
pin, the part will first erase the selected page in main memory (the erased state is a logic 1) and
then program the data stored in the buffer into the specified page in main memory. Both the
erase and the programming of the page are internally self-timed and should take place in a max-
imum time of tEP. During this time, the status register will indicate that the part is busy.
7.3 Buffer to Main Memory Page Program without Built-in Erase
A previously-erased page within main memory can be programmed with the contents of the buf-
fer. A 1-byte opcode, 88H, must be clocked into the device. For the DataFlash standard page
size (264-bytes), the opcode must be followed by three address bytes consist of six don’t care
bits, nine page address bits (PA8 - PA0) that specify the page in the main memory to be written
and nine don’t care bits. To perform a buffer to main memory page program without built-in
erase for the binary page size (256-bytes), the opcode 88H must be clocked into the device fol-
lowed by three address bytes consisting of seven don’t care bits, nine page address bits (A16 -
A8) that specify the page in the main memory to be written and eight don’t care bits. When a
low-to-high transition occurs on the CS pin, the part will program the data stored in the buffer
into the specified page in the main memory. It is necessary that the page in main memory that is
being programmed has been previously erased using one of the erase commands (Page Erase
or Block Erase). The programming of the page is internally self-timed and should take place in a
maximum time of tP. During this time, the status register will indicate that the part is busy.
7.4 Page Erase
The Page Erase command can be used to individually erase any page in the main memory array
allowing the Buffer to Main Memory Page Program to be utilized at a later time. To perform a
page erase in the DataFlash standard page size (264-bytes), an opcode of 81H must be loaded
into the device, followed by three address bytes comprised of six don’t care bits, nine page
address bits (PA8 - PA0) that specify the page in the main memory to be erased and nine don’t
care bits. To perform a page erase in the binary page size (256-bytes), the opcode 81H must be
loaded into the device, followed by three address bytes consist of seven don’t care bits, nine
page address bits (A16 - A8) that specify the page in the main memory to be erased and 8 don’t
care bits. When a low-to-high transition occurs on the CS pin, the part will erase the selected
page (the erased state is a logical 1). The erase operation is internally self-timed and should
take place in a maximum time of tPE. During this time, the status register will indicate that the
part is busy.
7.5 Block Erase
A block of eight pages can be erased at one time. This command is useful when large amounts
of data has to be written into the device. This will avoid using multiple Page Erase Commands.
To perform a block erase for the DataFlash standard page size (264-bytes), an opcode of 50H
must be loaded into the device, followed by three address bytes comprised of six don’t care bits,
six page address bits (PA8 -PA3) and 12 don’t care bits. The six page address bits are used to
specify which block of eight pages is to be erased. To perform a block erase for the binary page
size (256-bytes), the opcode 50H must be loaded into the device, followed by three address
bytes consisting of seven don’t care bits, six page address bits (A16 - A11) and 11 don’t care
bits. The six page address bits are used to specify which block of eight pages is to be erased.
When a low-to-high transition occurs on the CS pin, the part will erase the selected block of eight
pages. The erase operation is internally self-timed and should take place in a maximum time of
tBE. During this time, the status register will indicate that the part is busy.
8 AT45DB011D
3639K–DFLASH–6/2014







AT45DB011D-MH-SL954 equivalent, schematic
9.1.3
Read Sector Protection Register Command
To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has
been asserted, an opcode of 32H and three dummy bytes must be clocked in via the SI pin. After
the last bit of the opcode and dummy bytes have been clocked in, any additional clock pulses on
the SCK pins will result in data for the content of the Sector Protection Register being output on
the SO pin. The first byte corresponds to sector 0 (0a, 0b), the second byte corresponds to sec-
tor 1, the third byte corresponds to sector 2, and the last byte (byte 4) corresponds to sector 3.
Once the last byte of the Sector Protection Register has been clocked out, any additional clock
pulses will result in undefined data being output on the SO pin. The CS must be deasserted to
terminate the Read Sector Protection Register operation and put the output into a high-imped-
ance state.
Table 9-6. Read Sector Protection Register Command
Command
Read Sector Protection Register
Note: xx = Dummy Byte
Byte 1
32H
Byte 2
xxH
Byte 3
xxH
Byte 4
xxH
Figure 9-4. Read Sector Protection Register
CS
SI
Opcode
X
X
X
SO
Each transition
represents 8 bits
Data Byte
n
Data Byte
n+1
Data Byte
n+3
9.1.4
Various Aspects About the Sector Protection Register
The Sector Protection Register is subject to a limit of 10,000 erase/program cycles. Users are
encouraged to carefully evaluate the number of times the Sector Protection Register will be
modified during the course of the applications’ life cycle. If the application requires that the Sec-
tor Protection Register be modified more than the specified limit of 10,000 cycles because the
application needs to temporarily unprotect individual sectors (sector protection remains enabled
while the Sector Protection Register is reprogrammed), then the application will need to limit this
practice. Instead, a combination of temporarily unprotecting individual sectors along with dis-
abling sector protection completely will need to be implemented by the application to ensure that
the limit of 10,000 cycles is not exceeded.
16 AT45DB011D
3639K–DFLASH–6/2014










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