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PDF ( 数据手册 , 数据表 ) AT25DN256

零件编号 AT25DN256
描述 2.3V Minimum SPI Serial Flash Memory
制造商 Adesto
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AT25DN256 数据手册, 描述, 功能
AT25DN256
256-Kbit, 2.3V Minimum
SPI Serial Flash Memory with Dual-Read Support
Features
PRELIMINARY DATASHEET
Single 2.3V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.5ms Typical Page Program (256 Bytes) Time
40ms Typical 4-Kbyte Block Erase Time
320ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
350nA Ultra Deep Power Down current (Typical)
5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
6mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6mm)
8-lead TSSOP Package
DS-25DN256–039B–5/2014







AT25DN256 pdf, 数据表
Figure 7-2. Read Array - 0Bh Opcode
S
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
K
OPCODE
ADDRESS BITS A23-A0
DON'T CARE
I 0 0 0 0 1 0 1 1AAAAAA
AAAXXXXXXXX
MSB
MSB
MSB
DATA BYTE 1
O HIGH-IMPEDANCE
DDDDDDDDDD
MSB
MSB
7.2 Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has
been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two
bits of data to be clocked out of the device on every clock cycle, rather than just one.
The Dual-Output Read Array command can be used at any clock frequency, up to the maximum specified by fRDDO. To
perform the Dual-Output Read Array operation, the CS pin must first be asserted and then the opcode 3Bh must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must
also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the SO and SIO pins. The data is always output with the MSB of a byte first and the MSB is always output
on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same
data byte is output on the SIO pin. During the next clock cycle, bits five and four of the first data byte are output on the SO
and SIO pins, respectively. The sequence continues with each byte of data being output after every four clock cycles.
When the last byte (FFFFFh) of the memory array has been read, the device will continue reading from the beginning of
the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the
array.Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a high-impedance state.
The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 7-3. Dual-Output Read Array
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6, 6,2
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'21 7 &$5(
287387
287387
'$7$%<7( '$7$%<7(
       $$$$$$
06%
06%
$ $ $ ; ; ; ; ; ; ; ; ' ' ' ' ' ' ' ' ' '
06%
+,*+,03('$1&(
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06%
AT25DN256
DS-25DN256–039B–5/2014
8







AT25DN256 equivalent, schematic
The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the contents of
the buffer will be altered from its previous state when this command is issued.
Figure 10-1. Program OTP Security Register
CS
SCK
SI
SO
0123456789
29 30 31 32 33 34 35 36 37 38 39
OPCODE
ADDRESS BITS A23-A0
DATA IN BYTE 1
1 0 0 1 1 0 1 1AAA
MSB
MSB
AAADDDDDDDD
MSB
HIGH-IMPEDANCE
DATA IN BYTE n
DDDDDDDD
MSB
10.2
Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum
clock frequency specified by fCLK. To read the OTP Security Register, the CS pin must first be asserted and the opcode
of 77h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in
to specify the starting address location of the first byte to read within the OTP Security Register. Following the three
address bytes, two dummy bytes must be clocked into the device before data can be output.
After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP
Security Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security Register has been
read, the device will continue reading back at the beginning of the register (000000h). No delays will be incurred when
wrapping around from the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can
be deasserted at any time and does not require that a full byte of data be read.
Figure 10-2. Read OTP Security Register
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36
OPCODE
ADDRESS BITS A23-A0
DON'T CARE
0 1 1 1 0 1 1 1AAAAAA
MSB
MSB
HIGH-IMPEDANCE
AAAXXXXXX
MSB
XXX
DATA BYTE 1
DDDDDDDDDD
MSB
MSB
AT25DN256
DS-25DN256–039B–5/2014
16










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