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PDF ( 数据手册 , 数据表 ) AT25DN011-XMHFGP-B

零件编号 AT25DN011-XMHFGP-B
描述 2.3V Minimum SPI Serial Flash Memory
制造商 Adesto
LOGO Adesto LOGO 


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AT25DN011-XMHFGP-B 数据手册, 描述, 功能
AT25DN011
1-Mbit, 2.3V Minimum
SPI Serial Flash Memory with Dual-Read Support
Features
PRELIMINARY DATASHEET
Single 2.3V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.5ms Typical Page Program (256 Bytes) Time
40ms Typical 4-Kbyte Block Erase Time
320ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
350nA Ultra Deep Power Down current (Typical)
5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
6mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6mm)
8-lead TSSOP Package
DS-25DN011–038B–5/2014







AT25DN011-XMHFGP-B pdf, 数据表
Table 6-1. Command Listing
Command
Page Erase
Block Erase (4 Kbytes)
Block Erase (32 Kbytes)
Chip Erase
Chip Erase (Legacy Command)
Byte/Page Program (1 to 256 Bytes)
Protection Commands
Write Enable
Write Disable
Security Commands
Program OTP Security Register
Read OTP Security Register
Status Register Commands
Read Status Register
Write Status Register Byte 1
Write Status Register Byte 2
Miscellaneous Commands
Reset
Read Manufacturer and Device ID
Read ID (Legacy Command)
Deep Power-Down
Resume from Deep Power-Down
Ultra Deep Power-Down
Opcode
81h 1000 0001
20h 0010 0000
52h 0101 0010
D8h 1101 1000
60h 0110 0000
C7h 1100 0111
62h 0110 0010
02h 0000 0010
Clock
Frequency
Up to 104MHz
Up to 104MHz
Up to 104MHz
Up to 104MHz
Up to 104MHz
Up to 104MHz
Up to 104MHz
Up to 104MHz
Address
Bytes
3
3
3
3
0
0
0
3
Dummy
Bytes
0
0
0
0
0
0
0
0
Data
Bytes
0
0
0
0
0
0
0
1+
06h 0000 0110 Up to 104MHz
0
0
0
04h 0000 0100 Up to 104MHz
0
0
0
9Bh 1001 1011 Up to 104MHz
77h 0111 0111 Up to 104MHz
3
3
0 1+
2 1+
05h 0000 0101 Up to 104MHz
01h 0000 0001 Up to 104MHz
31h 0011 0001 Up to 104MHz
0
0
0
0 1+
01
01
F0h 1111 0000 Up to 104MHz
9Fh 1001 1111 Up to 104MHz
15h 0001 0101 Up to 104MHz
B9h 1011 1001 Up to 104MHz
ABh 1010 1011 Up to 104MHz
79h 0111 1001 Up to 104MHz
0
0
0
0
0
0
0 1(D0h)
0 1 to 4
02
00
00
00
AT25DN011
DS-25DN011–038B–5/2014
8







AT25DN011-XMHFGP-B equivalent, schematic
first be deasserted, and the BPL bit in the Status Register must be reset back to the logical “0” state using the Write
Status Register command.
If the WP pin is permanently connected to GND, then once the BPL bit is set to a logical “1”, the only way to reset the bit
back to the logical “0” state is to power-cycle the device. This allows a system to power-up with all sectors software
protected but not hardware locked. Therefore, sectors can be unprotected and protected as needed and then hardware
locked at a later time by simply setting the BPL bit in the Status Register.
When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the BPL bit in the Status Register can
be set to a logical “1”, but doing so will not lock the BP0 bit.
Table 9-2 details the various protection and locking states of the device.
Table 9-2. Hardware and Software Locking
WP BPL Locking BPL Change Allowed
00
Can be modified from 0 to 1
0
1
Hardware
Locked
Locked
10
Can be modified from 0 to 1
11
Can be modified from 1 to 0
BP0 and Protection Status
BP0 bit unlocked and modifiable using the Write
Status Register command. Memory array can be
protected and unprotected freely.
BP0 bit locked in current state. The Write Status
Register command will have no affect. Memory
array is locked in current protected or unprotected
state.
BP0 bit unlocked and modifiable using the Write
Status Register command. Memory array can be
protected and unprotected freely.
BP0 bit unlocked and modifiable using the Write
Status Register command. Memory array can be
protected and unprotected freely.
10. Security Commands
10.1
Program OTP Security Register
The device contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such
as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. The OTP
Security Register is independent of the main Flash memory array and is comprised of a total of 128 bytes of memory
divided into two portions. The first 64 bytes (byte locations 0 through 63) of the OTP Security Register are allocated as a
one-time user-programmable space. Once these 64 bytes have been programmed, they cannot be erased or
reprogrammed. The remaining 64 bytes of the OTP Security Register (byte locations 64 through 127) are factory
programmed by Adesto and will contain a unique value for each device. The factory programmed data is fixed and
cannot be changed.
Table 10-1. OTP Security Register
Security Register
Byte Number
0 1 . . . 62 63 64 65 . . . 126 127
One-Time User Programmable
Factory Programmed by Adesto
AT25DN011
DS-25DN011–038B–5/2014
16










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