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PDF ( 数据手册 , 数据表 ) AT25DF641A-MH-Y

零件编号 AT25DF641A-MH-Y
描述 2.7V Minimum SPI Serial Flash Memory
制造商 Adesto
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AT25DF641A-MH-Y 数据手册, 描述, 功能
AT25DF641A
64-Mbit, 2.7V Minimum SPI Serial Flash Memory
with Dual–I/O Support
Features
DATASHEET
Single 2.7V - 3.6V supply
Serial Peripheral Interface (SPI) compatible
Supports SPI Modes 0 and 3
Supports RapidSoperation
Supports Dual-Input Program and Dual-Output Read
Very high operating frequencies
100MHz for RapidS
85MHz for SPI
Clock-to-output time (tV) of 5ns maximum
Flexible, optimized erase architecture for code + data storage applications
Uniform 4KB, 32KB, and 64KB Block Erase
Full Chip Erase
Individual sector protection with Global Protect/Unprotect feature
128 Sectors of 64KB each
Hardware controlled locking of protected sectors via WP pin
Sector Lockdown
Make any combination of 64KB sectors permanently read-only
128-byte One-Time Programmable (OTP) Security Register
64 bytes factory preprogrammed
64 bytes user programmable
Flexible programming
Byte/Page Program (1 to 256 bytes)
Fast program and erase times
2.5ms typical Page Program (256 bytes) time
75ms typical 4KB Block Erase time
300ms typical 32KB Block Erase time
600ms typical 64KB Block Erase time
Program and Erase Suspend/Resume
Automatic checking and reporting of erase/program failures
Software controlled reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low power dissipation
25mA Active Read current (typical at 20MHz)
5μA Deep Power-Down current (typical)
Endurance: 100,000 program/erase cycles
Data retention: 20 years
Complies with full industrial temperature range
Industry standard green (Pb/Halide-free/RoHS compliant) package options
8-lead SOIC (0.208” wide)
8-pad Ultra-thin DFN (5 x 6 x 0.6mm)
8793D–DFLASH–5/2013







AT25DF641A-MH-Y pdf, 数据表
Table 6-1. Command Listing
Command
Read Commands
Read Array
Dual-Output Read Array
Program and Erase Commands
Block Erase (4KB)
Block Erase (32KB)
Block Erase (64KB)
Chip Erase
Byte/Page Program (1 to 256 bytes)
Dual-Input Byte/Page Program (1 to 256 bytes)
Program/Erase Suspend
Program/Erase Resume
Protection Commands
Write Enable
Write Disable
Protect Sector
Unprotect Sector
Global Protect/Unprotect
Read Sector Protection Registers
Security Commands
Sector Lockdown
Freeze Sector Lockdown State
Read Sector Lockdown Registers
Program OTP Security Register
Read OTP Security Register
Status Register Commands
Read Status Register
Write Status Register Byte 1
Write Status Register Byte 2
Miscellaneous Commands
Reset
Read Manufacturer and Device ID
Deep Power-Down
Resume from Deep Power-Down
Opcode
Clock
Frequency
Address Dummy Data
Bytes Bytes Bytes
1Bh 0001 1011 Up to 100MHz
0Bh 0000 1011 Up to 85MHz
03h 0000 0011 Up to 40MHz
3Bh 0011 1011 Up to 65MHz
3
3
3
3
2 1+
1 1+
0 1+
1 1+
20h 0010 0000 Up to 100MHz
52h 0101 0010 Up to 100MHz
D8h 1101 1000 Up to 100MHz
60h 0110 0000 Up to 100MHz
C7h 1100 0111 Up to 100MHz
02h 0000 0010 Up to 100MHz
A2h 1010 0010 Up to 100MHz
B0h 1011 0000 Up to 100MHz
D0h 1101 0000 Up to 100MHz
3
3
3
0
0
3
3
0
0
00
00
00
00
00
0 1+
0 1+
00
00
06h 0000 0110 Up to 100MHz
0
0
04h 0000 0100 Up to 100MHz
0
0
36h 0011 0110 Up to 100MHz
3
0
39h 0011 1001 Up to 100MHz
3
0
Use Write Status Register Byte 1 Command
3Ch 0011 1100 Up to 100MHz
3
0
0
0
0
0
1+
33h 0011 0011 Up to 100MHz
34h 0011 0100 Up to 100MHz
35h 0011 0101 Up to 100MHz
9Bh 1001 1011 Up to 100MHz
77h 0111 0111 Up to 100MHz
3
3
3
3
3
01
01
0 1+
0 1+
2 1+
05h 0000 0101 Up to 100MHz
01h 0000 0001 Up to 100MHz
31h 0011 0001 Up to 100MHz
0
0
0
0 1+
01
01
F0h 1111 0000 Up to 100MHz
9Fh 1001 1111 Up to 85 MHz
B9h 1011 1001 Up to 100 MHz
ABh 1010 1011 Up to 100 MHz
0
0
0
0
01
0 1 to 4
00
00
AT25DF641A [DATASHEET]
8793D–DFLASH–5/2013
8







AT25DF641A-MH-Y equivalent, schematic
8.3 Block Erase
A block of 4KB, 32KB, or 64KB can be erased (all bits set to the Logical 1 state) in a single operation by using one of
three different opcodes for the Block Erase command. A 20h opcode is used for a 4KB erase, a 52h opcode is used for a
32KB erase, and a D8h opcode is used for a 64KB erase. Before a Block Erase command can be started, the Write
Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a Logical 1
state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be
clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the
4KB, 32KB, or 64KB block to be erased must be clocked in. Any additional data clocked into the device will be ignored.
When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally
self-timed and should take place in a time of tBLKE.
Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the
device. Therefore, for a 4KB erase, address bits A11-A0 will be ignored by the device and their values can be either a
Logical 1 or 0. For a 32KB erase, address bits A14-A0 will be ignored, and for a 64KB erase, address bits A15-A0 will be
ignored. Despite the lower order address bits not being decoded by the device, the complete three address bytes must
still be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase operation will be performed.
If the address specified by A23-A0 points to a memory location within a sector that is in the protected or locked down
state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has
been deasserted.
The WEL bit in the Status Register will be reset back to the Logical 0 state if the erase cycle aborts due to an incomplete
address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the
region to be erased is protected or locked down.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBLKE time to
determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status
Register will be reset back to the Logical 0 state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase properly. If
an erase error occurs, it will be indicated by the EPE bit in the Status Register.
Figure 8-5. Block Erase
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
26 27 28 29 30 31
Opcode
Address Bits A23-A0
CCCCCCCCAAAAAA
MSB
MSB
AAAAAA
High-impedance
AT25DF641A [DATASHEET]
8793D–DFLASH–5/2013
16










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