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PDF ( 数据手册 , 数据表 ) AT25DF321A

零件编号 AT25DF321A
描述 32-Megabit 2.7-volt MinimumSPI Serial Flash Memory
制造商 ATMEL Corporation
LOGO ATMEL Corporation LOGO 


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AT25DF321A 数据手册, 描述, 功能
Features
Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
– Supports RapidS® Operation
– Supports Dual-Input Program and Dual-Output Read
Very High Operating Frequencies
– 100 MHz for RapidS
– 85 MHz for SPI
– Clock-to-Output (tV) of 5 ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– 64 Sectors of 64-Kbytes Each
Hardware Controlled Locking of Protected Sectors via WP Pin
Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
128-Byte Programmable OTP Security Register
Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
– 1.0 ms Typical Page Program (256 Bytes) Time
– 50 ms Typical 4-Kbyte Block Erase Time
– 250 ms Typical 32-Kbyte Block Erase Time
– 400 ms Typical 64-Kbyte Block Erase Time
Program and Erase Suspend/Resume
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 5 mA Active Read Current (Typical at 20 MHz)
– 5 µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (208-mil wide)
– 8-pad Ultra Thin DFN (5 x 6 x 0.6 mm)
32-Megabit
2.7-volt
Minimum
SPI Serial Flash
Memory
AT25DF321A
Preliminary
1. Description
The AT25DF321A is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25DF321A, with its erase granularity as small as
4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
3686C–DFLASH–12/08







AT25DF321A pdf, 数据表
Table 6-1. Command Listing
Command
Read Commands
Read Array
Dual-Output Read Array
Program and Erase Commands
Block Erase (4 KBytes)
Block Erase (32 KBytes)
Block Erase (64 KBytes)
Chip Erase
Byte/Page Program (1 to 256 Bytes)
Dual-Input Byte/Page Program (1 to 256 Bytes)
Program/Erase Suspend
Program/Erase Resume
Protection Commands
Write Enable
Write Disable
Protect Sector
Unprotect Sector
Global Protect/Unprotect
Read Sector Protection Registers
Security Commands
Sector Lockdown
Freeze Sector Lockdown State
Read Sector Lockdown Registers
Program OTP Security Register
Read OTP Security Register
Status Register Commands
Read Status Register
Write Status Register Byte 1
Write Status Register Byte 2
Miscellaneous Commands
Reset
Read Manufacturer and Device ID
Deep Power-Down
Resume from Deep Power-Down
Opcode
Clock
Frequency
Address Dummy
Bytes
Bytes
1Bh 0001 1011 Up to 100 MHz
0Bh 0000 1011 Up to 85 MHz
03h 0000 0011 Up to 50 MHz
3Bh 0011 1011 Up to 85 MHz
3
3
3
3
2
1
0
1
20h 0010 0000 Up to 100 MHz
52h 0101 0010 Up to 100 MHz
D8h 1101 1000 Up to 100 MHz
60h 0110 0000 Up to 100 MHz
C7h 1100 0111 Up to 100 MHz
02h 0000 0010 Up to 100 MHz
A2h 1010 0010 Up to 100 MHz
B0h 1011 0000 Up to 100 MHz
D0h 1101 0000 Up to 100 MHz
3
3
3
0
0
3
3
0
0
0
0
0
0
0
0
0
0
0
06h 0000 0110 Up to 100 MHz
0
0
04h 0000 0100 Up to 100 MHz
0
0
36h 0011 0110 Up to 100 MHz
3
0
39h 0011 1001 Up to 100 MHz
3
0
Use Write Status Register Byte 1 Command
3Ch 0011 1100 Up to 100 MHz
3
0
33h 0011 0011 Up to 100 MHz
34h 0011 0100 Up to 100 MHz
35h 0011 0101 Up to 100 MHz
9Bh 1001 1011 Up to 100 MHz
77h 0111 0111 Up to 100 MHz
3
3
3
3
3
0
0
0
0
2
05h 0000 0101 Up to 100 MHz
01h 0000 0001 Up to 100 MHz
31h 0011 0001 Up to 100 MHz
0
0
0
0
0
0
F0h 1111 0000 Up to 100 MHz
9Fh 1001 1111 Up to 85 MHz
B9h 1011 1001 Up to 100 MHz
ABh 1010 1011 Up to 100 MHz
0
0
0
0
0
0
0
0
Data
Bytes
1+
1+
1+
1+
0
0
0
0
0
1+
1+
0
0
0
0
0
0
1+
1
1
1+
1+
1+
1+
1
1
1
1 to 4
0
0
8 AT25DF321A [Preliminary]
3686C–DFLASH–12/08







AT25DF321A equivalent, schematic
The device also incorporates an intelligent erase algorithm that can detect when a byte location
fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status
Register.
Figure 8-5. Block Erase
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
26 27 28 29 30 31
OPCODE
ADDRESS BITS A23-A0
CCCCCCCCAAAAAA
MSB
MSB
AAAAAA
HIGH-IMPEDANCE
8.4 Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command.
Before a Chip Erase command can be started, the Write Enable command must have been pre-
viously issued to the device to set the WEL bit of the Status Register to a logical “1” state.
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in
device functionality when utilizing the two opcodes, so they can be used interchangeably. To
perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device.
Since the entire memory array is to be erased, no address bytes need to be clocked into the
device, and any data clocked in after the opcode will be ignored. When the CS pin is deas-
serted, the device will erase the entire memory array. The erasing of the device is internally self-
timed and should take place in a time of tCHPE.
The complete opcode must be clocked into the device before the CS pin is deasserted, and the
CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no
erase will be performed. In addition, if any sector of the memory array is in the protected or
locked down state, then the Chip Erase command will not be executed, and the device will return
to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be
reset back to the logical “0” state if the CS pin is deasserted on uneven byte boundaries or if a
sector is in the protected or locked down state.
While the device is executing a successful erase cycle, the Status Register can be read and will
indicate that the device is busy. For faster throughput, it is recommended that the Status Regis-
ter be polled rather than waiting the tCHPE time to determine if the device has finished erasing. At
some point before the erase cycle completes, the WEL bit in the Status Register will be reset
back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location
fails to erase properly. If an erase error occurs, it will be indicated by the EPE bit in the Status
Register.
16 AT25DF321A [Preliminary]
3686C–DFLASH–12/08










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