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PDF ( 数据手册 , 数据表 ) HCPL-0710500

零件编号 HCPL-0710500
描述 40 ns Prop. Delay/ SO-8 Optocoupler
制造商 Agilent(Hewlett-Packard)
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HCPL-0710500 数据手册, 描述, 功能
H
40 ns Prop. Delay,
SO-8 Optocoupler
Technical Data
HCPL-0710
Features
• +5 V CMOS Compatibility
• 8 ns max. Pulse Width
Distortion
• 20 ns max. Prop. Delay Skew
• High Speed: 12 Mbd
• 40 ns max. Prop. Delay
• 10 kV/µs Minimum Common
Mode Rejection
• 0°C to 85°C Temp. Range
• Safety and Regulatory
Approvals
UL Recognized
2500 V rms for 1 min. per
UL 1577
CSA Component Acceptance
Notice #5
Description
Available in the SO-8 package
style, the HCPL-0710 optocoupler
utilizes the latest CMOS IC
technology to achieve outstanding
performance with very low power
consumption. The HCPL-0710
requires only two bypass
capacitors for complete CMOS
compatability.
Basic building blocks of the
HCPL-0710 are a CMOS LED
driver IC, a high speed LED and a
CMOS detector IC. A CMOS logic
input signal controls the LED
driver IC which supplies current
to the LED. The detector IC
incorporates an integrated
photodiode, a high-speed
transimpedance amplifier, and a
voltage comparator with an
output driver.
Functional Diagram
**VDD1 1
8 VDD2**
Applications
• Digital Fieldbus Isolation:
DeviceNet, SDS, Profibus
• AC Plasma Display Panel
Level Shifting
• Multiplexed Data
Transmission
• Computer Peripheral
Interface
• Microprocessor System
Interface
VI 2
*3
GND1 4
LED1
SHIELD
7 NC*
IO
6 VO
5 GND2
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
*Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally. External connections to pin 7 are not recommended.
**A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component
to prevent damage and/or degradation which may be induced by ESD.







HCPL-0710500 pdf, 数据表
Propagation Delay, Pulse-
Width Distortion and
Propagation Delay Skew
Propagation Delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
tion delay from low to high (tPLH)
is the amount of time required for
an input signal to propagate to
the output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (tPHL) is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low. See
Figure 13.
INPUT
VI
OUTPUT
VO
10%
tPLH
90%
Figure 13.
tPHL
50%
90%
10%
5 V CMOS
0V
VOH
2.5 V CMOS
VOL
Pulse-width distortion (PWD) is
the difference between tPHL and
tPLH and often determines the
maximum data rate capability of a
transmission system. PWD can be
expressed in percent by dividing
the PWD (in ns) by the minimum
pulse width (in ns) being trans-
mitted. Typically, PWD on the
order of 20 - 30% of the minimum
pulse width is tolerable. The PWD
specification for the HCPL-0710
is 8 ns (10%) maximum across
recommended operating condi-
tions. 10% maximum is dictated
by the most stringent of the three
fieldbus standards, PROFIBUS.
Propagation delay skew, tPSK, is
an important parameter to con-
sider in parallel data applications
where synchronization of signals
on parallel data lines is a concern.
If the parallel data is being sent
through a group of optocouplers,
differences in propagation delays
will cause the data to arrive at the
outputs of the optocouplers at
different times. If this difference
in propagation delay is large
enough it will determine the
maximum rate at which parallel
data can be sent through the
optocouplers.
Propagation delay skew is defined
as the difference between the
minimum and maximum propa-
gation delays, either tPLH or tPHL,
for any given group of optocoup-
lers which are operating under
the same conditions (i.e., the
same drive current, supply volt-
age, output load, and operating
temperature). As illustrated in
Figure 14, if the inputs of a group
of optocouplers are switched
either ON or OFF at the same
time, tPSK is the difference
between the shortest propagation
delay, either tPLH or tPHL, and the
longest propagation delay, either
tPLH or tPHL.
As mentioned earlier, tPSK can
determine the maximum parallel
data transmission rate. Figure 15
is the timing diagram of a typical
parallel data application with both
the clock and data lines being
sent through the optocouplers.
The figure shows data and clock
signals at the inputs and outputs
of the optocouplers. In this case
the data is assumed to be clocked
off of the rising edge of the clock.







HCPL-0710500 equivalent, schematic
H
For technical assistance or the location of
your nearest Hewlett-Packard sales office,
distributor or representative call:
Americas/Canada: 1-800-235-0312 or
408-654-8675
Far East/Australasia: Call your local HP
sales office.
Japan: (81 3) 3335-8152
Europe: Call your local HP sales office.
Data subject to change.
Copyright © 1997 Hewlett-Packard Co.
Printed in U.S.A. 5965-6033E (1/97)










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