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PDF ( 数据手册 , 数据表 ) AT25BCM512B

零件编号 AT25BCM512B
描述 512-Kilobit 2.7-volt Minimum SPI Serial Flash Memory
制造商 Adesto
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AT25BCM512B 数据手册, 描述, 功能
Features
Single 2.7V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
70 MHz Maximum Operating Frequency
– Clock-to-Output (tV) of 6 ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
– 2.5 ms Typical Page Program (256 Bytes) Time
– 100 ms Typical 4-Kbyte Block Erase Time
– 500 ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 6 mA Active Read Current (Typical at 20 MHz)
– 5 µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-pad Ultra Thin DFN (2 x 3 x 0.6 mm)
1. Description
The AT25BCM512B is a serial interface Flash memory device designed for use in a
wide variety of high-volume consumer based applications in which program code is
shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25BCM512B, with its erase granularity as small as
4 Kbytes, makes it ideal for data storage as well, eliminating the need for additional
data storage EEPROM devices.
The erase block sizes of the AT25BCM512B have been optimized to meet the needs
of today's code and data storage applications. By optimizing the size of the erase
blocks, the memory space can be used much more efficiently. Because certain code
modules and data storage segments must reside by themselves in their own erase
regions, the wasted and unused memory space that occurs with large sectored and
large block erase Flash memory devices can be greatly reduced. This increased
memory space efficiency allows additional code routines and data storage segments
to be added while still maintaining the same overall device density.
The device also contains a specialized OTP (One-Time Programmable) Security Reg-
ister that can be used for purposes such as unique device serialization, system-level
Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 3-volt systems, the AT25BCM512B supports read,
program, and erase operations with a supply voltage range of 2.7V to 3.6V. No sepa-
rate voltage is required for programming and erasing.
512-Kilobit
2.7-volt
Minimum
SPI Serial Flash
Memory
AT25BCM512B
Preliminary
3704BX–DFLASH–11/2012







AT25BCM512B pdf, 数据表
8. Program and Erase Commands
8.1 Byte/Page Program
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of
data to be programmed into previously erased memory locations. An erased memory location is
one that has all eight bits set to the logical “1” state (a byte value of FFh). Before a Byte/Page
Program command can be started, the Write Enable command must have been previously
issued to the device (see “Write Enable” on page 11) to set the Write Enable Latch (WEL) bit of
the Status Register to a logical “1” state.
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device
followed by the three address bytes denoting the first byte location of the memory array to begin
programming at. After the address bytes have been clocked in, data can then be clocked into the
device and will be stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page
boundary (A7-A0 are not all 0), then special circumstances regarding which memory locations to
be programmed will apply. In this situation, any data that is sent to the device that goes beyond
the end of the page will wrap around back to the beginning of the same page. For example, if the
starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device,
then the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while
the last byte of data will be programmed at address 000000h. The remaining bytes in the page
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased
state (FFh). In addition, if more than 256 bytes of data are sent to the device, then only the last
256 bytes sent will be latched into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and pro-
gram it into the appropriate memory array locations based on the starting address specified by
A23-A0 and the number of data bytes sent to the device. If less than 256 bytes of data were sent
to the device, then the remaining bytes within the page will not be programmed and will remain
in the erased state (FFh). The programming of the data bytes is internally self-timed and should
take place in a time of tPP or tBP if only programming a single byte.
The three address bytes and at least one complete byte of data must be clocked into the device
before the CS pin is deasserted, and the CS pin must be deasserted on even byte boundaries
(multiples of eight bits); otherwise, the device will abort the operation and no data will be pro-
grammed into the memory array. In addition, if the memory is in the protected state (see “Block
Protection” on page 12), then the Byte/Page Program command will not be executed, and the
device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Sta-
tus Register will be reset back to the logical “0” state if the program cycle aborts due to an
incomplete address being sent, an incomplete byte of data being sent, the CS pin being deas-
serted on uneven byte boundaries, or because the memory location to be programmed is
protected.
While the device is programming, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled
rather than waiting the tBP or tPP time to determine if the data bytes have finished programming.
At some point before the program cycle completes, the WEL bit in the Status Register will be
reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte
location fails to program properly. If a programming error arises, it will be indicated by the EPE
bit in the Status Register.
8 AT25BCM512B [Preliminary]
3704BX–DFLASH–11/2012







AT25BCM512B equivalent, schematic
10.2
Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array oper-
ation up to the maximum clock frequency specified by fCLK. To read the OTP Security Register,
the CS pin must first be asserted and the opcode of 77h must be clocked into the device. After
the opcode has been clocked in, the three address bytes must be clocked in to specify the start-
ing address location of the first byte to read within the OTP Security Register. Following the
three address bytes, two dummy bytes must be clocked into the device before data can be
output.
After the three address bytes and the dummy bytes have been clocked in, additional clock
cycles will result in OTP Security Register data being output on the SO pin. When the last byte
(00007Fh) of the OTP Security Register has been read, the device will continue reading back at
the beginning of the register (000000h). No delays will be incurred when wrapping around from
the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-imped-
ance state. The CS pin can be deasserted at any time and does not require that a full byte of
data be read.
Figure 10-2. Read OTP Security Register
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36
OPCODE
ADDRESS BITS A23-A0
DON'T CARE
0 1 1 1 0 1 1 1AAAAAA
MSB
MSB
HIGH-IMPEDANCE
AAAXXXXXX
MSB
XXX
DATA BYTE 1
DDDDDDDDDD
MSB
MSB
11. Status Register Commands
11.1
Read Status Register
The Status Register can be read to determine the device’s ready/busy status, as well as the sta-
tus of many other functions such as Hardware Locking and Block Protection. The Status
Register can be read at any time, including during an internally self-timed program or erase
operation.
To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be
clocked into the device. After the opcode has been clocked in, the device will begin outputting
Status Register data on the SO pin during every subsequent clock cycle. After the last bit (bit 0)
of the Status Register has been clocked out, the sequence will repeat itself starting again with bit
7 as long as the CS pin remains asserted and the clock pin is being pulsed. The data in the Sta-
tus Register is constantly being updated, so each repeating sequence will output new data.
Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin
into a high-impedance state. The CS pin can be deasserted at any time and does not require
that a full byte of data be read.
16 AT25BCM512B [Preliminary]
3704BX–DFLASH–11/2012










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