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PDF ( 数据手册 , 数据表 ) HCPL-0708

零件编号 HCPL-0708
描述 High Speed CMOS Optocoupler
制造商 Agilent(Hewlett-Packard)
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HCPL-0708 数据手册, 描述, 功能
Agilent HCPL-0708
High Speed
CMOS Optocoupler
Data Sheet
Description
Available in SO-8 package, the
HCPL-0708 optocoupler utilizes the
latest CMOS IC technology to
achieve outstanding performance
with very low power consumption.
Basic building blocks of the HCPL-
Functional Diagram
NC 1
ANODE 2
8 VDD
7 NC
0708 are a high speed LED and a
CMOS detector IC. The detector
incorporates an integrated
photodiode, a high-speed trans-
impedance amplifier, and a voltage
comparator with an output driver.
Features
• +5 V CMOS compatibility
• 15 ns typical pulse width distortion
• 30 ns max. pulse width distortion
• 40 ns max. propagation delay
skew
• High speed: 15 MBd
• 60 ns max. propagation delay
• 10 kV/µs minimum common mode
rejection
• –40 to 100°C temperature range
• Safety and regulatory approvals
pending
– UL recognized
2500 V rms for 1 min. per
UL 1577 for HCPL-0708
– CSA component acceptance
Notice #5
– VDE 0884 (TUV) approved for
HCPL-0708 Option 060
CATHODE 3
NC 4
6 VO
5 GND
TRUTH TABLE
LED
OFF
ON
VO, OUTPUT
H
L
*A 0.1 µF bypass capacitor
must be connected between
pins 5 and 8.
Applications
• Scan drive in PDP
• Digital field bus isolation:
DeviceNet, SDS, Profibus
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
• DC/DC converter
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.







HCPL-0708 pdf, 数据表
Application Information
Bypassing and PC Board Layout
The HCPL-0708 optocoupler is
extremely easy to use. No
external interface circuitry is
required because the HCPL-0708
uses high-speed CMOS IC
technology allowing CMOS logic
to be connected directly to the
inputs and outputs.
As shown in Figure 6, the only
external component required for
proper operation is the bypass
capacitor. Capacitor values
should be between 0.01 µF and
0.1 µF. For each capacitor, the
total lead length between both
ends of the capacitor and the
power-supply pins should not
exceed 20 mm. Figure 7
illustrates the recommended
printed circuit board layout for
the HPCL-0708.
1
VI 2
3
4
8 VDD
C
7 NC
6 VO
5 GND
C1, C2 = 0.01 µF TO 0.1 µF
Figure 6. Recommended printed circuit board layout.
VDD
VI
C2
VO
GND
C1, C2 = 0.01 µF TO 0.1 µF
Figure 7. Recommended printed circuit board layout.
Propagation Delay, Pulse-Width
Distortion and Propagation Delay
Skew
Propagation Delay is a figure of
merit which describes how
quickly a logic signal propagates
through a system. The propaga-
tion delay from low to high (tPLH)
is the amount of time required for
an input signal to propagate to
the output, causing the output to
change from low to high.
Similarly, the propagation delay
from high to low (tPHL) is the
amount of time required for the
input signal to propagate to the
output, causing the output to
change from high to low. See
Figure 8.
INPUT
VI
OUTPUT
VO
10%
tPLH
90%
Figure 8.
8
tPHL
50%
90%
10%
5 V CMOS
0V
VOH
2.5 V CMOS
VOL














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