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PDF ( 数据手册 , 数据表 ) GW3887AIK-TK

零件编号 GW3887AIK-TK
描述 Wireless LAN Integrated Medium Access Controller
制造商 Conexant
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GW3887AIK-TK 数据手册, 描述, 功能
GW3887A
Wireless LAN Integrated Medium Access Controller with
Baseband Processor
The Conexant GW3887A Wireless LAN Integrated Media Access Controller
with Baseband Processor is part of both the PRISM GT™ single band and
PRISM WWR™ dual band radio chip sets. The GW3887A directly interfaces
with Conexant’s ISL3686B Single Band Direct Conversion Transceiver.
Adding Conexant’s ISL3084 5GHz VCO and ISL3980 Power Amp completes
an end-to-end WLAN chip set solution compliant with 802.11b/g standards.
Additionally, the GW3887A directly interfaces with Conexant’s ISL3692 Dual
Band Direct Conversion Transceiver. Adding Conexant’s ISL3092 11GHz
VCO and ISL3992 Dual Band Power Amp completes an end-to-end WLAN
chip set solution compliant with 802.11a/b/g/h/i/j standards. The 802.11
protocol is implemented in firmware supporting custom WLAN solutions.
The GW3887A improvements over the GW3887 include the addition of an
internal 48MHz oscillator, which eliminates several external components
from the radio design.
Software implements the full IEEE 802.11 Wireless LAN MAC protocol. It
supports BSS and IBSS operation under DCF, and operation under the
optional Point Coordination Function (PCF). Active scanning is performed
autonomously once initiated by host command. Host interface command
and status handshakes allow concurrent operations from multi-threaded I/
O drivers.
Orthogonal Frequency Division Multiplexing (OFDM) of 52 sub-carriers
modulated with BPSK, QPSK, 16QAM or 64QAM and a variety of
convolutional coding rates provides 8 selectable data rates at 2.4GHz and
5GHz. Differential phase shift keying modulation schemes, DBPSK and
DQPSK with data scrambling capability along with Complementary Code
Keying provide an additional 4 selectable data rates at 2.4GHz.
Built-in flexibility allows the GW3887A to be configured for a range of
applications. The MAC is based on the ARM 946E processor core that
offers a wide variety of code development support tools.
The GW3887A is housed in a thin plastic BGA package suitable for USB
2.0 Wireless LAN small form factor circuit card applications.
Features
• Firmware implements the full IEEE
802.11a/b/g/h/i/j Wireless LAN MAC
protocols
• Internal WEP Engine allows 64 or 128 bit
Encryption
• AES Hardware Accelerator
• Start-up modes allow the USB vendor and
device ID to be initialized from a small
external serial EEPROM. This allows
firmware to be downloaded from the host.
• On-chip SRAM memory
• A low frequency crystal oscillator can
maintain time, which allows the high
frequency clock source to be powered off
during sleep mode.
• Firmware controlled antenna diversity
• Data Rates: 1, 2, 5.5, 6, 9, 11, 12, 18, 24,
36, 48, & 54Mbps
• Modulation: OFDM with BPSK, QPSK,
16QAM, 64QAM; DBPSK; DQPSK and
CCK
• Convolutional coding and interleaving on
all OFDM rates
• Targeted for OFDM Multipath Delay
Spreads >800ns for 6Mbps, and >100ns
for 54Mbps
• Targeted for CCK Multipath Delay
Spreads >90ns at 11Mbps, >200ns at
5.5Mbps and >360ns at 1 and 2Mbps
• Direct interface with the ISL3692 and
ISL3686 Direct Conversion transceiver
• USB 2.0 Wireless LAN Adapters
A/D
BB
PROCESSOR
MAC
USB
2.0
Interface
D/A
GW3887A
SRAM
Figure 1: Simplified Block Diagram
Preliminary Data Sheet
November 12, 2004
Conexant Systems, Inc.
Proprietary - Use Pursuant to NDA
DO-406971-DS
Issue 2







GW3887AIK-TK pdf, 数据表
GW3887A Data Sheet
November 12, 2004
Table 3: Electrical Specificationsa (Sheet 2 of 2)
Parameter
Symbol Test Conditions
AC Electrical Specifications
CLOCK SIGNAL TIMING
OSC Clock Frequency (40MHz ±20ppm max, duty
cycle 45/55)
SYNTHESIZER
tCYC
SYNTHCLK(GP1-5) Width Hi
SYNTHCLK(GP1-5) Width Hi
Synthesizer Data Setup Time (SYNDATA, GP1-6)
Synthesizer Data Hold Time
LE pulse width (LE_IF, GP1-1 and LE_RF GP1-2)
tSCLKHI
tSCLKLO
tSYNSETUP
tSYNHOLD
tLE
a. Controlled via design or process parameters and not directly tested.
Min Typ Max Units
- 40 -
50 - -
50 - -
50 - -
10 - -
50 - -
MHz
ns
ns
ns
ns
ns
4 MAC Overview
The GW3887A MAC uses an ARM946E-S core. The MAC
is capable of operating at frequencies from 32kHz in a
reduced functionality power save mode up to 80MHz in
normal operation.
The GW3887A is equipped with on chip memory, which is
used for instruction memory and data buffers. No external
SRAM is required.
The GW3887A is designed for use with a USB 2.0 host
interface in accordance with the USB 2.0 specification.
The GW3887A is designed for device side applications.
The TMSEL[3:0] signals are used to select special test
modes and are unterminated for standard applications.
The GW3887A is equipped with 31 general purpose I/Os.
These GPIOs are divided into two groups, GP1[15:0] and
GP2[14:0]. In general, the GP1 I/Os are used for radio
control functions while the GP2 can be used for additional
features under firmware control.
5 Hardware WEP Engine
The Wired Equivalent Privacy Module (WEP) accelerates
data encryption and decrypting providing a level of
security for a wireless network that is intended to be at
least as good as that of a wired network. The encryption
protocol used is RSA RC4. For more information about
the WEP RC4 encryption, see IEEE Std. 802.11 1994
section 8.2.
6 Serial EEPROM Interface
The GW3887A allows the USB vendor ID and product ID
information and a small firmware image to be transferred
from an off-chip serial non-volatile memory device to on-chip
RAM after a system reset. This allows a system vendor
specific configuration. The operating frequency of the
serial port is 400kHz with a voltage of 3.3V.
PULL-UP
GW3887A GP2-1 (SD)
GP2-0 (SCL)
SDA
SCL
AO
A1
A2
WP
24C64 (NOTE)
NOTE: Must operate at 400kHz at 3.3VDC.
Figure 2: Small Serial EEPROM Interface
7 Reset
Power-on reset must be asserted via the RESET# pin to
the GW3887A until 10µs after establishing acceptable
power supply levels and stable clock signals. The
TMSEL[0.3] are sampled on the rising edge of RESET# to
determine the boot mode. These pins have internal pull
down resistors with an effective resistance of about 50K.
8 Baseband Processor Interface
The interface to the baseband processor is mostly
internal, but some of the connections are visible on the
GP2 and test ports when properly configured.
Conexant Systems, Inc.
DO-406971-DS
8
Proprietary - Use Pursuant to NDA
Issue 2














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