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PDF ( 数据手册 , 数据表 ) WT61P6

零件编号 WT61P6
描述 Embedded Micro-Controller
制造商 Weltrend
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WT61P6 数据手册, 描述, 功能
Weltrend Semiconductor, Inc.
WT61P6
Embedded Micro-Controller for Monitor
(Flash Memory Type)
Data Sheet
REV. 1.01
Oct 26, 2004
The information in this document is subject to change without notice.
Weltrend Semiconductor, Inc. All Rights Reserved.
2F, No. 24, Industry E. 9th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan
TEL:886-3-5780241 FAX:886-3-5794278.5770419







WT61P6 pdf, 数据表
WT61P6 v1.01
Monitor Controller
I/O Port
I/O Port A
The PA0 and PA1 are general purpose IO shared with DDC interface and 8031 UART interface. They
are the IO port only when both ENDDC and REN are “0”. If the PA0OE is “1”, Pin PA0 is an open-drain
output port. If the PA0OE is “0”, Pin PA0 is an input port without internal pull-up resistor. The PA1 is
the same as the PA0. Fig. 2 shows the structure of PA0.
INTERNAL_DATA_BUS
DATA[0]
D Q PA0OE
WRITE_PA_CTRL
C QN
R
RESET
PA0
DATA[0]
D Q PA0O
WRITE_PA_DATA C
RESET
QN
R
READ_PA_DATA
DATA[0]
Fig.2 Structure of PA0, PA1,PA2,PA3
The PA4 to PA7 are general purpose IO shared with PWM output and some special functions. When
the EPWMn is “0” and the special function is disabled, PAn is a general purpose I/O port. If the PAnOE
is “1”, the PAn is configured as an output port in a push-pull type which can source or sink 6mA. If the
PAnOE is “0”, the PAn is configured as an input port with internal pull-up resistor.
INTERNAL_DATA_BUS
DATA[2]
D Q PA2OE
WRITE_PA_CTRL
C QN
R
RESET
PA2
DATA[2]
D Q PA2O
WRITE_PA_DATA C
RESET
QN
R
READ_PA_DATA
DATA[2]
Fig.3 Structure of PA4
Weltrend Semiconductor, Inc.
Page 8







WT61P6 equivalent, schematic
WT61P6 v1.01
Monitor Controller
Sync Processor Control Register
The HV_CR1 and HV_CR2 control the HOUT, VOUT and Clamp model.
Name Addr R/W Initial Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
HV_CR1 0011h W 00h ENHOUT ENVOUT HOPOL VOPOL QUICK SEPART ENFREE ENPAT
HV_CR2 0012h W 00h ENCLP CLPEG CLPPO CLPPW1 CLPPW0 SOG HVPASS BYPASS
Bit Name
Description
ENHOUT
“1”: Enable HOUT.
“0”: Disable HOUT. Pin is configured as I/O port PD1.
ENVOUT
“1”: Enable VOUT.
“0”: Disable VOUT. Pin is configured as I/O port PD0.
HOPOL
“1”: HOUT is positive polarity.
“0”: HOUT is negative polarity.
VOPOL
“1”: VOUT is positive polarity.
“0”: VOUT is negative polarity.
QUICK
“1”: Select 16ms time interval to count H pulses every 16.384ms.
“0”: Select 32ms time interval to count H pulses every 32.768ms.
When H+V mode, the falling edge of extracted Vsync is synchronized with Hsync leading
SEPART
edge.
“1”: Enable sync separator circuit and use the extracted Vsync signal as VOUT.
“0”: VOUT pin outputs Vsync from VIN pin
ENFREE Enable free-running sync signal output on HOUT and VOUT pins when this bit is set.
ENPAT
“1”: Enable self-test pattern output on PAT pin when this bit is set.
“0”: Disable test pattern output. Pin is configured as I/O port PB3.
ENCLP
“1”: Enable clamp pulse output on CLAMP pin.
“0”: Disable clamp pulse output. Pin is configured as I/O port PA7.
CLPEG
“1”: Clamp pulse follows HOUT signal’s rising edge.
“0”: Clamp pulse follows HOUT signal’s falling edge.
CLPPO
“1”: Clamp pulse is positive polarity.
“0”: Clamp pulse is negative polarity.
(CLPPW1,CLPPW0)=(0,0) : clamp pulse width=125ns – 208ns
CLPPW1 ~ (CLPPW1,CLPPW0)=(0,1) : clamp pulse width=208ns – 292ns
CLPPW2 (CLPPW1,CLPPW0)=(1,0) : clamp pulse width=458ns – 542ns
(CLPPW1,CLPPW0)=(1,1) : clamp pulse width=958ns – 1042ns
Select composite sync signal input source.
SOG “1” : Composite sync signal comes from SOGIN pin.
“0” : Composite sync signal comes from HIN pin.
Select bypass HSYNC & VSYNC.
HVPASS “1” : HOUT = HIN & VOUT=VIN without polarity changed.
“0” : HOUT = HIN & VOUT=VIN with polarity changed.
Select bypass the composite signal separator or not.
BYPASS “1” : HOUT pin outputs sync signal bypass the composite signal separator.
“0” : HOUT pin outputs sync signal from the composite signal separator.
Weltrend Semiconductor, Inc.
Page 16










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