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PDF ( 数据手册 , 数据表 ) GD25Q64B

零件编号 GD25Q64B
描述 Uniform Sector Dual and Quad Serial Flash
制造商 GigaDevice
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GD25Q64B 数据手册, 描述, 功能
Uniform Sector
Dual and Quad Serial Flash
GD25Q64B
GD25Q64B
DATASHEET
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GD25Q64B pdf, 数据表
Uniform Sector
Dual and Quad Serial Flash
4. DEVICE OPERATION
GD25Q64B
SPI Mode
Standard SPI
The GD25Q64B features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (CS#),
Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the
rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The GD25Q64B supports Dual SPI operation when using the Dual Output Fast Readand Dual I/O Fast Read
(3BH and BBH) commands. These commands allow data to be transferred to or from the device at two times the rate of the
standard SPI. When using the Dual SPI command the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
Quad SPI
The GD25Q64B supports Quad SPI operation when using the Quad Output Fast Read,Quad I/O Fast Read,
Quad I/O Word Fast Read(6BH, EBH, E7H) commands. These commands allow data to be transferred to or from the
device at four times the rate of the standard SPI. When using the Quad SPI command the SI and SO pins become
bidirectional I/O pins: IO0 and IO1, and WP# and HOLD# pins become IO2 and IO3. Quad SPI commands require the
non-volatile Quad Enable bit (QE) in Status Register to be set.
Hold
The HOLD# signal goes low to stop any serial communications with the device, but doesnt stop the operation of write
status register, programming, or erasing in progress.
The operation of HOLD, need CS# keep low, and starts on falling edge of the HOLD# signal, with SCLK signal being
low (if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge
of HOLD# signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low).
The SO is high impedance, both SI and SCLK dont care during the HOLD operation, if CS# drives high during HOLD
operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and
then CS# must be at low.
Figure1. Hold Condition
CS#
SCLK
HOLD#
HOLD
HOLD
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GD25Q64B equivalent, schematic
Uniform Sector
Dual and Quad Serial Flash
GD25Q64B
7.1. Write Enable (WREN) (06H)
The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL)
bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE) and Write Status
Register (WRSR) command. The Write Enable (WREN) command sequence: CS# goes low sending the Write Enable
command CS# goes high.
Figure2. Write Enable Sequence Diagram
CS#
SCLK
01234567
Command
SI
06H
High-Z
SO
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit. The Write Disable command sequence:
CS# goes lowSending the Write Disable command CS# goes high. The WEL bit is reset by following condition:
Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase
commands.
Figure3. Write Disable Sequence Diagram
CS#
SCLK
SI
SO
01234567
Command
04H
High-Z
7.3. Read Status Register (RDSR) (05H or 35H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read at
any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in
progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to the device. It is
also possible to read the Status Register continuously. For command code 05H, the SO will output Status Register bits
S7~S0. The command code 35H, the SO will output Status Register bits S15~S8.
Figure4. Read Status Register Sequence Diagram
CS#
SCLK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
05H or 35H
High-Z
S7~S0 or S15~S8 out
S7~S0 or S15~S8 out
7654321076543210
MSB
16
MSB
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