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PDF ( 数据手册 , 数据表 ) TDA3683

零件编号 TDA3683
描述 Multiple voltage regulator
制造商 NXP Semiconductors
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TDA3683 数据手册, 描述, 功能
TDA3683
Multiple voltage regulator with switch and ignition buffer
Rev. 02 — 7 October 2005
Product data sheet
1. General description
The TDA3683 is a multiple output voltage regulator with a power switch and an
ignition buffer. Several protections and diagnostic options are incorporated in this
design.
The TDA3683 is primarily developed to cover the complete power supply
requirements in car radio applications.
The standby regulators (regulators 1, 2 and 3) are especially designed to supply
digital circuitry that has to be permanently connected e.g. Controller Area Network
(CAN) bus, Digital Signal Processor (DSP) core and the microcontroller. In
combination with the reset delay capacitor (pin RDC1 or pin RDC2/3) and the reset
function (pin RST1 or pin RST2/3), a proper start-up sequence for a microcontroller is
guaranteed. The storage capacitor (pin STC) makes the standby regulator outputs
insensitive for short battery drops (e.g. during engine start-up).
The switched regulators (regulators 4, 5, 6 and 7) are intended to be used as supply
for the tuner, logic, sound processor and CD / tape control.
The power switch (pin PSW) can be used for switching the electrically powered
antenna, display unit and CD / tape drives.
The ignition buffer is intended to produce a clean logic output signal when a polluted
ignition key signal is used as input.
2. Features
s Three enable pin controlled standby regulators:
x REG1: 5 V / 600 mA controlled by the EN1 input
x REG2: 3.3 V / 200 mA controlled by the EN2/3 input
x REG3: 1.9 V / 150 mA controlled by the EN2/3 input
s Four mode pin controlled switched regulators:
x REG4: 8.5 V / 350 mA
x REG5: 5 V / 1.8 A
x REG6: 3.3 V / 1.2 A
x REG7: 2.4 V to 10 V / 2 A adjustable using external resistor divider
s One mode pin controlled power switch; 2.2 A continuous and 3 A surge, with delayed
lower current limit so as to be less sensitive to inrush currents
s One independent ignition buffer (inverted output, open-collector) with good input
protection against high transients
s A storage capacitor is included to provide back-up supply for the standby regulators in
the event of loss of battery supply







TDA3683 pdf, 数据表
Philips Semiconductors
TDA3683
Multiple voltage regulator with switch and ignition buffer
7.5 Storage capacitor
The storage capacitor (pin STC) is used as a back-up supply for the standby regulators
when the battery (pins VP1 / VP2) can no longer provide the supply. This situation may
occur for cold weather engine starts. The rising and falling storage capacitor voltage
threshold levels determine if the standby regulators can be switched on.
The storage capacitor pin is not intended to be used as an output (e.g. supply switch). No
external load should be connected to this pin.
7.6 Reset delay capacitors
The reset delay capacitors (pins RDC1 and RDC2/3) are used to delay the reset pulse
(RST1 and RST2/3) starting from the time the associated standby regulator output voltage
comes within its regulated voltage range i.e. crosses the rising reset threshold level. An
internal current source is used to charge the reset delay capacitor. The reset output will be
released (output goes HIGH) when the voltage on the reset delay capacitor crosses the
rising threshold level.
If the associated standby regulator voltage drops out of its regulated voltage range (drops
below its falling reset threshold level) the reset delay capacitor will be discharged with a
relatively high sink current. The reset output will be activated (output goes LOW) when the
reset delay capacitor crosses the falling threshold level. This feature is included to secure
a smooth start-up of the microcontroller at first connection, without uncontrolled switching
of the relevant standby regulators during a start-up sequence. It should be noted that
RDC1 is also used as a time constant for the delayed current protection of the power
switch.
7.7 Reset outputs
The reset function depends on the reset delay capacitor voltage and includes hysteresis
to avoid oscillation at the threshold level. The reset outputs are push-pull for sourcing or
sinking current. The output voltage can be switched between the ground level and the
output voltage of the relevant standby regulator. An external reset delay capacitor can be
added if a timed reset pulse is required (CRDC1 or CRDC2/3).
Standby regulator 1 has an independent reset function (pins RST1 and RDC1). Standby
regulators 2 and 3 have combined circuitry (pins RST2/3 and RDC2/3). The reset trigger
signals from both regulators are connected using an OR function to the reset output buffer
thus ensuring that both regulators can generate a reset when appropriate. The RST1
output is linked to standby regulator 1 (5 V) and, therefore, generates a 5 V HIGH-level
output voltage. The RST2/3 output is linked to regulator 2 (3.3 V) and, therefore,
generates a 3.3 V HIGH-level output voltage.
7.8 Hold output
The hold output (pin HOLD) is a combined output for the thermal pre-warning signal and
all other diagnostic signals. To distinguish between these signals, the HOLD output is
designed as an active HIGH 3-state output buffer. When a no failure condition is present
the output is LOW. When a thermal pre-warning signal is generated (e.g. to shut down
other circuits in the radio before the regulator itself shuts down) the signal rises to its MID
TDA3683_2
Product data sheet
Rev. 02 — 7 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
8 of 31







TDA3683 equivalent, schematic
Philips Semiconductors
TDA3683
Multiple voltage regulator with switch and ignition buffer
Table 7: Characteristics …continued
VP1 = VP2 = 14.4 V; Tamb = 25 °C; RL= ∞ Ω; measured in test circuits of Figure 8; unless otherwise specified.
Symbol
Parameter
Conditions
Min Typ
Max
Unit
Vhys(REG5)
hysteresis voltage due
to regulator 5
- 0.2
-
V
Vth(r)(REG6)
rising threshold voltage VP1 and VP2 rising
of regulator 6
[2] -
VREG6 0.15 VREG6 0.075 V
Vth(f)(REG6)
falling threshold voltage VP1 and VP2 falling
of regulator 6
[2] 2.7
VREG6 0.3 -
V
Vhys(REG6)
hysteresis voltage due
to regulator 6
- 0.15
-
V
Vth(r)(VP)
Vth(f)(VP)
Vhys(VP)
rising threshold voltage VP1 and VP2 rising;
of supply voltage
VMODE < 0.8 V;
VEN1 or VEN2/3 > 2.4 V
falling threshold voltage VP1 and VP2 falling;
of supply voltage
VMODE < 0.8 V;
VEN1 or VEN2/3 > 2.4 V
hysteresis voltage of
supply voltage
7.8 8.4
7.7 8.1
- 0.3
9
8.5
-
V
V
V
Hold buffer
Vo(HOLD)(L)
LOW-level HOLD
output
0 0.1
0.6
V
Isink(L)
Vo(HOLD)(H)
LOW-level sink current
HIGH-level HOLD
output
VHOLD 0.6 V
0.5 -
6.0 7.0
-
8.0
mA
V
Isource(H)
HIGH-level source
current
VHOLD = 3.3 V
12
-
mA
Vo(HOLD)(M)
Isource(M)
MID-level HOLD output
MID-level source
current
VHOLD = 1.5 V
1.8 2.15
12
2.5
-
V
mA
tr rise time
tf fall time
Reset and Reset delay 1
CL = 50 pF
CL = 50 pF
- 7 50 µs
- 1 50 µs
Isink(L)
Isource(H)
tr
tf
Ich
Idch
Vth(r)(RDC1)
LOW-level sink current VRST1 0.8 V; VRDC1 < 1.0 V
HIGH-level source
current
VRST1 = 4.5 V;
VRDC1 > 3.5 V
rise time
CL = 50 pF
fall time
CL = 50 pF
charge current
VRDC1 = 0 V; VEN1 > 2.4 V
discharge current
VRDC1 = 3 V;
VP1 = VP2 = 4.3 V
reset delay capacitor 1
rising voltage threshold
2
240
-
-
2
1.0
[3] 2.5
-
400
7
1
4
1.6
3.0
-
900
50
50
8
-
3.5
mA
µA
µs
µs
µA
mA
V
Vth(f)(RDC1)
reset delay capacitor 1
falling voltage threshold
[3] 1.0
1.2
1.4
V
td(RST1)
delay time reset signal CRDC1 = 47 nF
[4] 20
35
70
ms
TDA3683_2
Product data sheet
Rev. 02 — 7 October 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
16 of 31










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