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PDF ( 数据手册 , 数据表 ) Am29LV200BB-120EIB

零件编号 Am29LV200BB-120EIB
描述 2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
制造商 Advanced Micro Devices
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Am29LV200BB-120EIB 数据手册, 描述, 功能
Am29LV200B
Data Sheet
The Am29LV200B is not offered for new designs. Please contact a Spansion representative for alter-
nates.
The following document contains information on Spansion memory products. Although the document
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appro and
changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 21521 Revision D Amendment 6 Issue Date October 10, 2006
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Am29LV200BB-120EIB pdf, 数据表
CONNECTION DIAGRAMS
NC 1
RY/BY# 2
NC 3
A7 4
A6 5
A5 6
A4 7
A3 8
A2 9
A1 10
A0 11
CE# 12
VSS 13
OE# 14
DQ0 15
DQ8 16
DQ1 17
DQ9 18
DQ2 19
DQ10 20
DQ3 21
DQ11 22
DATA SHEET
44 RESET#
43 WE#
42 A8
41 A9
40 A10
39 A11
38 A12
37 A13
36 A14
35 A15
34 A16
SO 33 BYTE#
32 VSS
31 DQ15/A-1
30 DQ7
29 DQ14
28 DQ6
27 DQ13
26 DQ5
25 DQ12
24 DQ4
23 VCC
48-ball FBGA
Top View, Balls Facing Down
A6 B6 C6 D6 E6 F6 G6 H6
A13 A12 A14 A15 A16 BYTE# DQ15/A-1 VSS
A5 B5 C5 D5 E5 F5 G5 H5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
A4 B4 C4 D4 E4 F4 G4 H4
WE# RESET# NC
NC
DQ5 DQ12 VCC
DQ4
A3 B3 C3 D3 E3 F3 G3 H3
RY/BY# NC NC NC DQ2 DQ10 DQ11 DQ3
A2 B2 C2 D2 E2 F2 G2 H2
A7
NC
A6
A5
DQ0
DQ8 DQ9
DQ1
A1 B1 C1 D1 E1 F1 G1 H1
A3 A4 A2 A1 A0 CE# OE# VSS
Special Handling Instructions
Special handling is required for Flash Memory products
in molded packages (TSOP, BGA, SSOP, PLCC,
PDIP). The package and/or data integrity may be com-
promised if the package body is exposed to
temperatures above 150°C for prolonged periods of
time.
6
Am29LV200B
21521D6 October 10, 2006







Am29LV200BB-120EIB equivalent, schematic
DATA SHEET
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 2. Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadver tent writes (refer to Table 5 for
command definitions). In addition, the following hard-
ware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than VLKO. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
14
Am29LV200B
21521D6 October 10, 2006










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