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PDF ( 数据手册 , 数据表 ) 74HCT123

零件编号 74HCT123
描述 Dual retriggerable monostable multivibrator
制造商 NXP Semiconductors
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74HCT123 数据手册, 描述, 功能
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
Rev. 10 — 3 December 2015
Product data sheet
1. General description
The 74HC123; 74HCT123 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC123; 74HCT123 are dual retriggerable monostable multivibrators with output
pulse width control by three methods:
1. The basic pulse is programmed by selection of an external resistor (REXT) and
capacitor (CEXT).
2. Once triggered, the basic output pulse width may be extended by retriggering the
gated active LOW-going edge input (nA) or the active HIGH-going edge input (nB). By
repeating this process, the output pulse period (nQ = HIGH, nQ = LOW) can be made
as long as desired. Alternatively an output delay can be terminated at any time by a
LOW-going edge on input nRD, which also inhibits the triggering.
3. An internal connection from nRD to the input gates makes it possible to trigger the
circuit by a HIGH-going signal at input nRD as shown in Table 3.
Schmitt-trigger action in the nA and nB inputs, makes the circuit highly tolerant to slower
input rise and fall times.
The 74HC123; 74HCT123 are identical to the 74HC423; 74HCT423 but can be triggered
via the reset input.
2. Features and benefits
DC triggered from active HIGH or active LOW inputs
Retriggerable for very long pulses up to 100 % duty factor
Direct reset terminates output pulse
Schmitt-trigger action on all inputs except for the reset input
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and from 40 C to +125 C







74HCT123 pdf, 数据表
NXP Semiconductors
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC123
tpd propagation nRD, nA, nB to nQ or nQ; [1]
delay
CEXT = 0 pF;
REXT = 5 k;
see Figure 9
VCC = 2.0 V
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
nRD (reset) to nQ or nQ;
CEXT = 0 pF;
REXT = 5 k;
see Figure 9
- 83 255
-
320
-
385 ns
- 30 51
-
64
-
77 ns
- 26 -
-
-
-
- ns
- 24 43
-
54
-
65 ns
VCC = 2.0 V
- 66 215
-
270
-
325 ns
VCC = 4.5 V
- 24 43
-
54
-
65 ns
VCC = 5 V; CL = 15 pF
- 20 -
-
-
-
- ns
VCC = 6.0 V
- 19 37
-
46
-
55 ns
tt transition time see Figure 9
[1]
VCC = 2.0 V
- 19 75
-
95
-
110 ns
VCC = 4.5 V
- 7 15
-
19
-
22 ns
VCC = 6.0 V
- 6 13
-
16
-
19 ns
tW pulse width nA LOW; see Figure 10
VCC = 2.0 V
100 8 - 125
-
150
- ns
VCC = 4.5 V
20 3 -
25
-
30
- ns
VCC = 6.0 V
17 2 -
21
-
26
- ns
nB HIGH; see Figure 10
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
nRD LOW; see Figure 11
100 17 -
125
-
150
- ns
20 6 -
25
-
30
- ns
17 5 -
21
-
26
- ns
VCC = 2.0 V
100 14 -
125
-
150
- ns
VCC = 4.5 V
20 5 -
25
-
30
- ns
VCC = 6.0 V
17 4 -
21
-
26
- ns
nQ HIGH and nQ LOW;
VCC = 5.0 V;
see Figure 10 and 11
[2]
CEXT = 100 nF;
REXT = 10 k
CEXT = 0 pF;
REXT = 5 k
- 450 -
-
-
-
- s
- 75 -
-
-
-
- ns
74HC_HCT123
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 3 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 24







74HCT123 equivalent, schematic
NXP Semiconductors
74HC123; 74HCT123
Dual retriggerable monostable multivibrator with reset
12.3 Power-down considerations
A large capacitor CEXT may cause problems when powering-down the monostable due to
the energy stored in this capacitor. When a system containing this device is
powered-down or a rapid decrease of VCC to zero occurs, the monostable may sustain
damage, due to the capacitor discharging through the input protection diodes. To avoid
this possibility, use a damping diode (DEXT) preferably a germanium or Schottky type
diode able to withstand large current surges and connect as shown in Figure 15.
'(;7
*1'


Q$  
Q%  
Fig 15. Power-down protection circuit
&(;7
5(;7
9&&
Q&(;7
 
Q5(;7&(;7
 
 
Q4
 
Q4
 
Q5'
DDD
74HC_HCT123
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 3 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
16 of 24










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