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PDF ( 数据手册 , 数据表 ) W78E054D

零件编号 W78E054D
描述 8-BIT MICROCONTROLLER
制造商 Nuvoton
LOGO Nuvoton LOGO 


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W78E054D 数据手册, 描述, 功能
W78E054D/W78E052D Data Sheet
1 GENERAL DESCRIPTION
The W78E054D/W78E052D series is an 8-bit microcontroller which can accommodate a wider fre-
quency range with low power consumption. The instruction set for the W78E054D/W78E052D series is
fully compatible with the standard 8052.
The W78E054D/W78E052D series contains 16K/8K bytes Flash EPROM programmable by hardware
writer; a 256 bytes RAM; four 8-bit bi-directional (P0, P1, P2, P3) and bit-addressable I/O ports; an ad-
ditional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. The-
se peripherals are supported by 8 sources 4-level interrupt capability. To facilitate programming and
verification, the Flash EPROM inside the W78E054D/W78E052D series allows the program memory to
be programmed and read electronically. Once the code is confirmed, the user can protect the code for
security.
The W78E054D/W78E052D series microcontroller has two power reduction modes, idle mode and
power-down mode, both of which are software selectable. The idle mode turns off the processor clock
but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for
minimum power consumption. The external clock can be stopped at any time and in any state without
affecting the processor. The W78E054D/W78E052D series contains In-System Programmable (ISP)
2KB LDROM for loader program, operating voltage from 3.3V to 5.5V.
Note: If the applied VDD is not stable, especially with long transition time of power on/off, it’s
recommended to apply an external RESET IC to the RST pin for improving the stability of sys-
tem.
-4-
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W78E054D pdf, 数据表
W78E054D/W78E052D Data Sheet
6 BLOCK DIAGRAM
P1.0
| Port 1
P1.7
Port 1
Latch
Interrupt
Timer
1
Timer
0
Timer
2
UART
ACC B
T1 Register
T2 Register
PSW
Stack
ALU Pointer
Instruction
Decoder
&
Sequencer
SFR & RAM
Address
256 bytes
RAM & SFR
Port 0
Latch
Port 0
P0.0
|
P0.7
DPTR
Timer Reg.
PC
Incrementor
Addr. Reg.
Flash EPROM
P3.0
|
P3.7
P4.0
|
P4.3
Port 3
Port 3
Latch
Port 4
Oscillator
Port 4
Latch
Oscillator
Selecter
Bus & Lock
Controller
Watchdog
Timer
Reset Block
Port 2
Latch
Port 2
Power Control
VCC GND
XTAL1 XTAL2
ALE /PSEN
RST
Figure 61 W78E054D/W78E052D Block Diagram
P2.0
|
P2.7
- 11 -
Publication Release Date: Aug 31, 2012
Revision A12







W78E054D equivalent, schematic
W78E054D/W78E052D Data Sheet
Special Function Registers:
SYMBOL
B
ACC
P4
PSW
TH2
TL2
RCAP2H
RCAP2L
T2MOD
T2CON
SFRCN
SFRRD
SFRAH
SFRAL
XICON
CHPCON
EAPAGE
IP
IPH
P3
IE
P2
SBUF
SCON
P1
WDTC
AUXR
TH1
TH0
TL1
TL0
TMOD
TCON
PCON
P0UPR
DPH
DPL
DEFINITION
ADDRESS MSB
B register
F0H (F7) (F6)
Accumulator
E0H
(E7) (E6)
Port 4
D8H
Program status word
D0H
(D7)
CY
(D6)
AC
T2 reg. high
CDH
T2 reg. low
CCH
T2 capture low
CBH
T2 capture high
CAH
Timer 2 Mode
C9
Timer 2 control
C8H
(CF)
TF2
(CE)
EXF2
SFR program of control
C7H
SFR program of data register
C6H
SFR program of address high byte C5H
SFR program of address low byte C4H
External interrupt control
C0H
PX3 EX3
Chip control
BFH
SWRST -
Erase page operation modes
BEH
Interrupt priority
B8H
(BF)
-
(BE)
-
Interrupt priority High
B7H
Port 3
B0H
(B7) (B6)
RD WR
Interrupt enable
A8H
(AF)
EA
(AE)
-
Port 2
A0H
(A7) (A6)
A15 A14
Serial buffer
99H
Serial control
98H (9F) (9E)
SM0/FE SM1
Port 1
90H (97) (96)
BIT ADDRESS, SYMBOL
(F5) (F4) (F3)
(E5) (E4) (E3)
INT2
(D5)
F0
(D4)
RS1
(D3)
RS0
(F2)
(E2)
INT3
(D2)
OV
(CD)
RCLK
NOE
(CC)
TCLK
NCE
(CB)
EXEN2
CTRL3
(CA)
TR2
CTRL2
IE3 IT3 PX2 EX2
---
(BD)
PT2
(BC)
PS
(BB)
PT1
(BA)
PX1
(B5)
T1
(AD)
ET2
(A5)
A13
(B4)
T0
(AC)
ES
(A4)
A12
(B3)
INT1
(AB)
ET1
(A3)
A11
(B2)
INT0
(AA)
EX1
(A2)
A10
(9D)
SM2
(95)
(9C)
REN
(94)
(9B)
TB8
(93)
(9A)
RB8
(92)
Watchdog control
Auxiliary
Timer high 1
Timer high 0
Timer low 1
Timer low 0
Timer mode
Timer control
Power control
Port 0 pull up option Register
Data pointer high
Data pointer low
8FH
8EH
8DH
8CH
8BH
8AH
89H
88H
87H
86H
83H
82H
ENW
CLRW WIDL -
-
PS2
----
GATE
(8F)
TF1
SMOD
-
C/T M1
(8E) (8D)
TR1 TF0
SMOD0 -
--
M0
(8C)
TR0
POR
-
GATE
(8B)
IE1
GF1
-
C/T
(8A)
IT1
GF0
-
(F1)
(E1)
(D1)
F1
(C9)
C/T2
CTRL1
IE2
ISP
EAPG1
(B9)
PT0
(B1)
TXD
(A9)
ET0
(A1)
A9
(99)
TI
(91)
T2EX
PS1
M1
(89)
IE0
PD
-
LSB RESET
(F0) 0000 0000B
(E0) 0000 0000B
0000 1111B
(D0)
P
0000 0000B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
DCEN 0000 0000B
(C8)
0000 0000B
CP/RL2
CTRL0 0000 0000B
0000 0000B
0000 0000B
0000 0000B
IT2 0000 0000B
ENP
0000 0000B
EAPG0 0000 0000B
(B8) 1100 0000B
PX0
0000 0000B
(B0)
RXD
1111 1111B
(A8) 0100 0000B
EX0
(A0) 1111 1111B
A8
0000 0000B
(98) 0000 0000B
RI
(90) 1111 1111B
T2
PS0 0000 0000B
ALEOFF 0000 0110B
0000 0000B
0000 0000B
0000 0000B
0000 0000B
M0 0000 0000B
(88) 0000 0000B
IT0
IDL 0011 0000B
P0UP 0000 0001B
0000 0000B
0000 0000B
- 19 -
Publication Release Date: Aug 31, 2012
Revision A12










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