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PDF ( 数据手册 , 数据表 ) AN10861

零件编号 AN10861
描述 GreenChip III TEA1752 integrated PFC and flyback controller
制造商 NXP Semiconductors
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AN10861 数据手册, 描述, 功能
AN10861
GreenChip III TEA1752 integrated PFC and flyback controller
Rev. 01 — 16 July 2010
Application note
Document information
Info Content
Keywords
GreenChip III, TEA1752, PFC, flyback, high efficiency, adaptor, notebook,
PC power
Abstract
The TEA1752 is a member of the new generation of PFC and flyback
combination controller ICs, used for efficient switched mode power
supplies. It has a high level of integration which allows the design of a
cost-effective power supply with a minimum number of external
components. The TEA1752 is fabricated in a Silicon On Insulator (SOI)
process, enabling it to operate a wide voltage range.
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AN10861 pdf, 数据表
NXP Semiconductors
AN10861
GreenChip III TEA1752 integrated PFC and flyback controller
Table 1. Pin description …continued
Pin Name
Functional description
14 PFCTIMER Timer pin to delay the turning off of the PFC when the load of the flyback is
removed or minimized.
The PFC is enabled when the voltage across this pin is low (1.27 V). It is
disabled when the voltage is high (3.6 V).
15 HVS
High-voltage safety spacer, not connected.
16 HV
High-voltage input for the internal start-up current source (output at pin 1)
and valley sensing of the flyback.
The combination of the demagnetization detection at the FBAUX pinand the
valley detection at the HV pin determine the switch-on moment of the
flyback in the valley.
3. System description and calculation
3.1 PFC and flyback start conditions
Figure 2 and Figure 3 show the conditions for enabling the PFC and the flyback. If start-up
problems occur these conditions can be checked to find the cause of the problem. Some
of the conditions are dynamic signals (see Figure 4) and should be checked with an
oscilloscope.
LATCH > 1.35 V
PFCSENSE (soft start) > 0.5 V
VINSENSE > 1.15 V
VOSENSE > 1.15 V
PFCCOMP > 3.5 V
fsw(fb)swon(PFC) > 86 kHz
AND
Fig 2. PFC start condition
enable PFC
019aaa028
LATCH > 1.35 V
FBSENSE (soft start) > 0.63 V
VOSENSE > 1.15 V
FBCTRL < 4.5 V
AND
Fig 3. Flyback start conditions
enable flyback
019aaa029
3.2 Start-up sequence
At switch-on with a low mains voltage the TEA1752 power supply has the following
start-up sequence (see Figure 4):
1. The HV current source is set to 1.0 mA and the VCC elcap is charged to 0.65 V to
detect a possible short circuit at pin VCC.
2. At VCC = 0.65 V, the HV current source is set to 5.4 mA and the VCC elcap is quickly
charged to Vth(UVLO).
3. At VCC = Vth(UVLO), the HV current source is set to 1.0 mA again and the VCC elcap is
charged to Vstartup.
4. At Vstartup, the HV current source is switched off and the 80 μA LATCH pin current
source is switched on to charge the LATCH pin capacitor. At the same time the
PFCSENSE and FBSENSE soft start current sources are switched on.
AN10861
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 16 July 2010
© NXP B.V. 2010. All rights reserved.
8 of 46







AN10861 equivalent, schematic
NXP Semiconductors
AN10861
GreenChip III TEA1752 integrated PFC and flyback controller
PFC stage
D1
C3
VO(PFC)
R5
1.5 μA
VINSENSE 2.2 V
9 VOSENSE
TEA1752
2
GND
C4
Fig 9. PFC output voltage setting
R6
place C4 and R7
as close as
possible to the IC
R7
019aaa035
Two resistors of 4.7 MΩ (1 %) can be used between the bulk elcap and the
VOSENSE pin. The dimensioning of the Ibst(dual) current source (15 μA) has been
adapted to the use of these resistor values. With a resistor value of 4.7 MΩ for R5 and R6
and 60 kΩ to 62 kΩ for R7 a universal mains adapter has a PFC output voltage of
approximately 380 V to 390 V at high mains and 240 V to 250 V at low mains.
The resistor R7 (1 %) between the VOSENSE pin and ground can be calculated with
Equation 5:
R7 = (---R----5----+-----R----6---)--×--V----r-e-g-(-V--O--S--E--N--S-E--)-
(VO(PFC) Vreg(VOSENSE))
Example with a regulated PFC output voltage of 382 V:
(5)
R7 ==-(-)4---.7---M---(-Ω)-3-8-+-2--4V-.-2-7---M--.-5Ω--V---×---2-.-5---V--- 62 kΩ ()1 %
At low mains the 15 μA current source Ibst(dual) is active. The lower PFC output voltage can
be calculated with Equation 6:
VO()PFC low
=
R---5--+-+-R--6------R--7---
R7
()Vre
g ()V OS
ENSE
Ibst ()dual
R7
(6)
Example for calculating the lower PFC output voltage:
R5 and R6 = 4.7 MΩ
R7 = 62 kΩ
VO()PFC low ==4--.-7--M---Ω-----+-+-46--.27---k-M-Ω--Ω------6---2--k--Ω--- ⋅ ()2.5 V15 μA 62 kΩ
240 V
The function of capacitor C4 at the VOSENSE pin is to filter noise and to prevent false
triggering of the protection modes because of MOSFET switching noise, mains surge
events or ElectroStatic Discharge (ESD) events. False triggering of the Vovp(VOSENSE)
protection can cause audible noise and disturbance of the AC mains input current. False
AN10861
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 16 July 2010
© NXP B.V. 2010. All rights reserved.
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