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PDF ( 数据手册 , 数据表 ) D8213

零件编号 D8213
描述 Dual High-Efficiency PWM Step-Down DC-DC Converter
制造商 iDESYN
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D8213 数据手册, 描述, 功能
iDESYN
D8213
Dual High-Efficiency
PWM Step-Down DC-DC Converter
General Description
The i D8213 is a dual high efficiency Pul se Width
Modulated ( PWM) step-down DC-DC c onverter. I t i s
capable o f delivering 1. 2A output curr ent o ver a w ide
input v oltage range f rom 2.6V t o 5.5V, t he i D8213 is
ideally s uited for port able electronic de vices that are
powered f rom 1-cell Li-ion battery or from ot her power
sources w ithin the range such as cel lular phones ,
PDAs and other handheld devices.
Two operat ional m odes are a vailable: PWM/Low-
Dropout auto-switch and shutdown m odes. Internal
synchronous rect ifier wi th low RDS(ON) dramatically
reduces conduct ion loss at P WM mode. No external
Schottky diode is required in practical application.
The i D8213 ent ers Low -Dropout mode w hen norm al
PWM cannot pro vide regulated out put voltage by
continuously t urning on t he upper PMOS. The iD8213
enter shutdo wn m ode and consum es less than 0. 1 A
when EN pin is pulled low.
The s witching ripple is easily smoothed-out by s mall
package fi ltering e lements due to a fixed operation
frequency of 1.5MHz. This along with small TDFN-12L
and T DFN-10 pac kage pr ovides small PCB ar ea
application. O ther f eatures i nclude soft start, l ower
internal r eference voltage w ith 3% accurac y, over
temperature protection, and over current protection.
Ordering Information
iD8213 -
Taping
Package R: Tape and Reel
FEC:TDFN-12L (3x3)
FEA:TDFN-10 (3x3)
Output Voltage Voltage Code
Adjustable
AD
Applications
Mobile Phones
Personal Information Appliances
Wireless and DSL Modems
MP3 Players
Portable Instruments
Features
2.6V to 5.5V Input Range
Adjustable Output Voltage
1.2A Output Current per Channel
95% Efficiency
No Schottky Diode Required
40 A Quiescent Current per Channel
1.5MHz Fixed-Frequency PWM Operation
Small TDFN-12 and TDFN-10 Package
RoHS Compliant and Green
Marking Information
For marking information, please contact our sales
representative directly or through distributor around
your location.
Jan. 2014
1
V0.2
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D8213 pdf, 数据表
iDESYN
iD8213
is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce t he most im provement. E fficiency can be
expressed as:
Efficiency = 100% (L1+ L2+ L3+...)
where L1, L2, etc. are the i ndividual loss es as a
percentage of input pow er. Although al l di ssipative
elements in the c ircuit produce l osses, two m ain
sources us ually account f or most of t he loss es: VIN
quiescent current and I2R losses.
The VIN quiescent current loss dominates the efficiency
loss at v ery l ow load currents w hereas the I 2R loss
dominates the eff iciency loss at medi um t o high load
currents. In a typical efficiency plot, the efficiency curve
at v ery low load cur rents can be misleading since the
actual power lost is of no consequence.
1.The V IN quiescent current appears due t o two
components : the DC bias current and the gate charge
currents. The gate charge current resul ts from
switching the gat e c apacitance o f the int ernal power
MOSFET sw itches. E ach time the gate is switched
from hi gh to low to high again, a packet of charge Q
moves from VIN to ground.
The resul ting Q/ t is the curr ent out o f VIN that is
typically larger than the DC bi as current. In continuous
mode,
IGATECHG = f(QT + QB)
where Q T and Q B are t he gat e char ges of the internal
top and bot tom switches. B oth t he DC bi as and gat e
charge l osses ar e propor tional to V IN and t hus their
effects w ill be more pronounced at higher suppl y
voltages.
2. I2R losses are calculated from the resistances of the
internal sw itches, R SW and e xternal i nductor RL. In
continuous m ode the a verage output current f lowing
through inductor L is choppedbetween t he m ain
switch and t he s ynchronous switch. Thus, the s eries
resistance looking into the SW pin is a f unction of both
top and botto m MOSFE T R DS(ON) and the dut y c ycle
(DC) is shown as follows :
RSW = RDS(ON)TOP x DC + RDS(ON)BOT x (1 DC)
The RDS(ON) for both the top and bottom MOSFETs can
be obt ained from the Typical P erformance
Characteristics curves. T hus, to obtai n I2R losses,
simply add R SW to RL and m ultiply the res ult by the
square of the average out put curr ent. O ther loss es
including C IN and C OUT ESR dissipative losses and
inductor core loss es general ly account f or l ess than
2% of the total loss.
Thermal Considerations
The maximum power di ssipation depends on t he
thermal resistance of IC package, PCB l ayout, the rate
of surroundings airflow and t emperature d ifference
between j unction to ambient. The maximum power
dissipation can be calculated by following formula :
PD(MAX) = ( TJ(MAX) TA ) / JA
Where TJ(MAX) is the maximum junction temperature, TA
is the ambient t emperature and the JA is the j unction
to am bient t hermal resistance. F or recomm ended
operating condi tions s pecification o f iD8213 DC/ DC
converter, where T J(MAX) is the maximum j unction
temperature of t he d ie and T A is the a mbient
temperature. The junc tion t o am bient t hermal
resistance JA is layout dependent. For T DFN-12L 3x3
packages, the thermal resistance JA is 48 C/W on the
standard JEDEC 51-7 f our-layers thermal t est board.
The maximum power di ssipation at TA = 25 C can be
calculated by following formula :
PD(MAX) = (125 C 25 C) / (48 C/W) = 2.083W for
TDFN-12L 3x3 packages
The maximum power dissipation depends on operat ing
ambient temperature f or fixed T J(MAX) and t hermal
resistance JA. For i D8213 pack ages, the F igure 4 o f
derating curves allows the designer to see the effect of
Jan. 2014
8
V0.2














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