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PDF ( 数据手册 , 数据表 ) ISL6366

零件编号 ISL6366
描述 Dual 6-Phase + 1-Phase PWM Controller
制造商 Intersil Corporation
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ISL6366 数据手册, 描述, 功能
Dual 6-Phase + 1-Phase PWM Controller for VR12/IMVP7
Applications
ISL6366
The ISL6366 is a dual PWM controller; its 6-phase PWMs control
the microprocessor core or memory voltage regulator, while its
single-phase PWM controls the peripheral voltage regulator for
graphics, system agent, or processor I/O.
The ISL6366 utilizes Intersil’s proprietary Enhanced Active Pulse
Positioning (EAPP) modulation scheme to achieve the extremely
fast transient response with fewer output capacitors.
The ISL6366 is designed to be compliant to Intel VR12/IMVP7
specifications. It accurately monitors the load current via the
IMON pin and reports this information via the IOUT register to
the microprocessor, which sends a PSI# signal to the controller
at low power mode via SVID bus. The controller enters 1- or
2-phase operation in low power mode (PSI1); in the ultra low
power mode (PSI2,3), it can further drop the number of phases
and enable the diode emulation ofthe operational phase.In low
power modes, the magnetic core and switching losses are
significantly reduced, yielding high efficiency at light load. After
the PSI# signal is de-asserted, the dropped phase(s) are added
back to sustain heavy load transient response and efficiency.
Today’s microprocessors require a tightly regulated output voltage
position versus load current (droop). The ISL6366 senses the
output current continuously by measuring thevoltage acrossthe
dedicated current sense resistor or the DCRof the output
inductor. The sensed current flows outof the FB pinto develop the
precision voltage drop across the feedback resistor for droop
control. Currentsensing circuitsalso provide the needed signals
for channel-currentbalancing, average overcurrent protection and
individual phase current limiting. TheTM and TMS pins are to
sense anNTC thermistor’s temperature, which is internally
digitizedfor thermal monitoring and for integrated thermal
compensation of the current sense elements of therespective
regulator.
The ISL6366 features remote voltage sensing and completely
eliminates any potential difference between remote and local
grounds. This improves regulation and protection accuracy. The
threshold-sensitive enable input is available to accurately
coordinate the start-up of the ISL6366 with other voltage rails.
Features
• Intel VR12/IMVP7 Compliant
- SerialVID with Programmable IMAX, TMAX, BOOT,
ADDRESS OFFSET Registers
• Intersil’s Proprietary Enhanced Active Pulse Positioning
(EAPP) Modulation Scheme, Patented
- Voltage Feed-forward and Ramp Adjustable Options
- High Frequency and PSI Compensation Options
- Variable Frequency Control During Load Transients to
Reduce Beat Frequency Oscillation
- Linear Control with Evenly Distributed PWM Pulses for
Better Phase Current Balance During Load Transients
•D ual Outputs
- Output 1 (VR0): 1 to 6-Phase, Coupled Inductor
Compatibility, for Core or Memory
- Output 2 (VR1): Single Phase for Graphics, System Agent,
or Processor I/O
- Differential Remote Voltage Sensing
- ±0.5% Closed-loop System Accuracy Over Load, Line and
Temperature
- Phase Doubler Compatibility (NOT Phase Dropping)
• Proprietary Active Phase Adding and Dropping with Diode
Emulation Scheme For Enhanced Light Load Efficiency
• Programmable Slew Rate of Fast Dynamic VID with
Dynamic VID Compensation (DVC) for VR0
• Dynamic VID Compensation (DVS) for VR1 at No Droop
• Droop and Diode Emulation Options
• Programmable 1 or 2-Phase Operation in PSI1/2/3 Mode
• Programmable Standard or Coupled-Inductor Operation
• Precision Resistor or DCR Differential Current Sensing
- Integrated Programmable Current Sense Resistors
- Integrated Thermal Compensation
- Accurate Load-Line (Droop) Programming
- Accurate Channel-Current Balancing
- Accurate Current Monitoring
• Average Overcurrent Protection and Channel Current Limit
With Internal Current Comparators
• Precision Overcurrent Protection on IMON & IMONS Pins
• Independent Oscillators, up to 1MHz Per Phase, for Cost,
Efficiency, and Performance Optimization
• Dual Thermal Monitoring and Thermal Compensation
• Start-up Into Pre-Charged Load
• Pb-Free (RoHS Compliant)
Janu ar y 3, 20 11
FN6964.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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ISL6366 pdf, 数据表
ISL6366
Absolute Maximum Ratings
VCC, VR_RDY, VR_RDYS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V
NC4, NC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V to 27V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V to VCC + 0.3V
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V ±5%
Ambient Temperature
ISL6366CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ISL6366IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Thermal Information
Thermal Resistance (Notes 4, 5)
θJA (°C/W) θJC (°C/W)
60 Ld 7x7 QFN Package . . . . . . . . . . . . . . .
24
1.5
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, VCC = 5V, Unless Otherwise specified. Boldface limits apply over the
operating temperature range.
PARAMETER
TEST CONDITIONS
MIN MAX
(Note 7) TYP (Note 7) UNITS
VOLTAGE REGULATOR (VR) ADDRESS
Multiple-Phase Voltage Regulator (VR0) ADDRESS Hexadecimal Format
0 EVN C
-
Single-Phase Voltage Regulator (VR1) ADDRESS Hexadecimal Format
1 ODD 7
-
VCC SUPPLY CURRENT
Nominal Supply
Shutdown Supply
POWER-ON RESET AND ENABLE
VCC = 5VDC; EN_PWR = 5VDC; RT = 125kΩ, ISEN1-6 = 0µA
VCC = 5VDC; EN_PWR = 0VDC; RT = 125kΩ
23
16.5
28 34.5
22 28.5
mA
mA
VCC Rising POR Threshold
4.30 4.40 4.50
V
VCC Falling POR Threshold
3.75 3.90 4.0
V
EN_PWR_FT Rising Threshold
0.830 0.850 0.870 V
EN_PWR_FT Falling Threshold
0.730 0.750 0.770 V
EN_VTT Rising Threshold
0.830 0.850 0.870 V
EN_VTT Falling Threshold
0.730 0.750 0.770 V
DAC (VID+OFFSET)
System Accuracy of ISL6366CRZ
(DAC = 1V to 2.155 V, TJ = 0°C to +70°C)
System Accuracy of ISL6366CRZ
(DAC = 0.8V to 1V, TJ = 0°C to +70°C)
System Accuracy of ISL6366CRZ
(DAC = 0.25V to 0.8V, TJ = 0°C to +70°C)
System Accuracy of ISL6366IRZ
(DAC = 1V to 2.155V, TJ = -40°C to +85°C)
System Accuracy of ISL6366IRZ
(DAC = 0.8V to 1V, TJ = -40°C to +85°C)
System Accuracy of ISL6366IRZ
(DAC = 0.25V to 0.8V, TJ = -40°C to +85°C)
(Note 6, Closed-Loop)
(Note 6, Closed-Loop)
(Note 6, Closed-Loop)
(Note 6, Closed-Loop)
(Note 6, Closed-Loop)
(Note 6, Closed-Loop)
-0.5 - 0.5 %VID
-5 - 5 mV
-8 - 8 mV
-0.6 - 0.6 %VID
-6 - 6 mV
-9 - 9 mV
8 FN6964.0
January 3, 2011







ISL6366 equivalent, schematic
ISL6366
The CPU can enter four distinct power states as shown in Table 2.
The ISL6366 supports all states, but it treats PSI2 and PSI3 the
same. In addition, the setDecay mode will automatically enter PSI2
State while decaying the output voltage. However, prior to the end of
soft-start (i.e: VR_RDY goes high), the lower power mode
(PSI1/2/3/Decay) is NOT enabled.
TABLE 2. POWER STATE COMMAND FROM CPU
STATE
DESCRIPTION
PSI0 High Power Mode, All Phases are running
PSI1 Low Power Mode
PSI2 Very Low Power Mode
PSI3 Ultra Low Power Mode, treated as PSI2
Decay Automatically entering PSI2 and Ramping down the output
voltage to a target voltage in Decay Mode
When the SVID bus sends PSI1/2/3 or Set VID Decay command, it
indicates the low power mode operation of the processor. The
controller will start phase shedding the next switching pulse. The
controller allows to drop the number of active phases according to
the logic on Table 3 for high light load efficiency performance. The
“NPSI” register and SICI pin are to program the controller in
operation of non-coupled (SI), 2-phase coupled, or (N-x)-Phase
coupled inductors. Different cases yield different PWM output
behaviors on both dropped phase(s) and operational phase(s) as
PSI# is asserted and de-asserted. When CPU sends PSI0 command,
it will pull the controller back to normal CCM PWM operation to
sustain an immediate heavy transient load and high efficiency. Note
that “N-x” means N-x phase coupled and x phase(s) are uncoupled.
For 2-Phase coupled inductor (CI) operation, both coupled phases
should be 180° out of phase. In low power states
(PSI1/2/3/Decay), the opposite phase of the operational phase
will turn on its Low-side MOSFET to circulate inductor current to
minimize conduction loss when Phase 1 is high.
When PSI1 is asserted, the VR0 is in single-phase CCM operation
with PWM1, or 2-phase CCM operation with PWM1 and 2, 3 or 4,
as shown in Table 1. The number of operational phases is
configured by “NPSI” register, shown in Table 3. In PSI2/3/Decay
State, only single phase is in DCM/CCM operation, which is
programmed by the “DE” register; the opposite PWM 2, 3, or 4
(depending upon configured maximum phase number as in
Table 1) of the PWM1 however will pull low at PWM1 high in CI
applications.
TABLE 3. PHASE DROPPING CONFIGURATION AT PSI1 AND
PSI2/3/DECAY
SICI NPSI CODE
PSI1 Mode
PSI2/3
& DECAY
0 0 SI1 SI, (N-1)-CI
1-Phase
1-Phase
0 1 SI2 SI, (N-2)-CI 2-Phase
1-Phase
1 0 CI1 2-Phase CI 1-Phase
1-Phase
1 1 CI2 2-Phase CI 2-Phase
1-Phase
NOTE: For 2-Phase CI option, the dropped coupled phase turns on LGATE
to circulate current when PWM1 is high.
The VR1 outputcan be disabled by pulling PWMS to VCC while the
respective address is released for use with a different VR controller.
For proper operation of VR0, the VR1’s respective pins should be
configured as described in “Disabling Output” on page 35.
While the controller is operational (VCC above POR, EN_VTT and
EN_PWR are both high, valid VID inputs), it can pull the PWM pins
to ~40% of VCC (~2V for 5V VCC bias) during various stages, such
as soft-start delay, phase shedding operation, or fault conditions
(OC or OV events). The matching driver's internal PWM resistor
divider can further raise the PWM potential, but not lower it
below the level set by the controller IC. Therefore, the controller's
PWM outputs are directly compatible with Intersil drivers that
require 5V PWM signal amplitudes. Drivers requiring 3.3V PWM
signal amplitudes are generally incompatible.
Diode Emulation Operation
To improve light efficiency, the ISL6366 canenter diode emulation
operation in PSI2/3 or Decay mode. Users however should select
Intersil VR12/IMVP7 compatible drivers: ISL6627 or ISL6625 for
PSI# channel(s). Thediode emulation should be disabledif
non-compatible power stages or drivers are used.
Switching Frequency
Both VR0 and VR1 can independently set switching frequency,
which is determined by the selection of the frequency-setting
resistor, RT, which is connected from FS or FSS pin to GND or
VCC. Equation 4 and Figure 4 are provided to assist in selecting
the correct resistor value.
RT = 5-----F----1S---0W---1---0--
(EQ. 4)
where FSW is the switching frequency of each phase.
Independent frequency for VR0 and VR1 allows for cost,
efficiency, and performance optimization. Proximity between the
power trains of the two regulators imposed by the
space-constrained layouts can lead to cross-coupling. To
minimize the effect of cross-coupling between regulators, select
operating frequencies at least 50kHz apart.
SWITCHING FREQUENCY (Hz)
FIGURE 4. SWITCHING FREQUENCY vs RT
16 FN6964.0
January 3, 2011










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