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PDF ( 数据手册 , 数据表 ) M93C76-x

零件编号 M93C76-x
描述 EEPROM
制造商 STMicroelectronics
LOGO STMicroelectronics LOGO 


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M93C76-x 数据手册, 描述, 功能
M93C86-x M93C76-x M93C66-x
M93C56-x M93C46-x
16-Kbit, 8-Kbit, 4-Kbit, 2-Kbit and 1-Kbit
(8-bit or 16-bit wide) MICROWIRE serial access EEPROM
Datasheet - production data
PDIP8 (BN)
SO8 (MN)
150 mil width
READY/BUSY signal during programming
2 MHz clock rate
Sequential read operation
Enhanced ESD/latch-up behavior
More than 4 million write cycles
More than 200-year data retention
Packages
– SO8, TSSOP8, UFDFPN8 packages:
RoHS-compliant and Halogen-free
(ECOPACK®)
– PDIP8 package:
RoHS-compliant (ECOPACK1®)
TSSOP8 (DW)
169 mil width
UFDFPN8 (MC)
2 x 3 mm
Features
Industry standard MICROWIRE bus
Single supply voltage:
– 2.5 V to 5.5 V for M93Cx6-W
– 1.8 V to 5.5 V for M93Cx6-R
Dual organization: by word (x16) or byte (x8)
Programming instructions that work on: byte,
word or entire memory
Self-timed programming cycle with auto-erase:
5 ms
Table 1. Device summary
Reference
Part Memory
number
size
Supply
voltage
M93C46-x
M93C46-W
M93C46-R
2.5 V to 5.5 V
1 Kbit
1.8 V to 5.5 V
M93C56-x
M93C56-W
M93C56-R
2.5 V to 5.5 V
2 Kbit
1.8 V to 5.5 V
M93C66-x
M93C66-W
M93C66-R
2.5 V to 5.5 V
4 Kbit
1.8 V to 5.5 V
- M93C76-R 8 Kbit 1.8 V to 5.5 V
M93C86-x
M93C86-W
M93C86-R
2.5 V to 5.5 V
16 Kbit
1.8 V to 5.5 V
November 2013
This is information on a product in full production.
DocID4997 Rev 15
1/33
www.st.com
http://www.Datasheet4U.com







M93C76-x pdf, 数据表
Connecting to the serial bus
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x
2 Connecting to the serial bus
Figure 3 shows an example of three memory devices connected to an MCU, on a serial bus.
Only one device is selected at a time, so only one device drives the Serial Data output (Q)
line at a time, the other devices are high impedance.
The pull-down resistor R (represented in Figure 3) ensures that no device is selected if the
bus master leaves the S line in the high impedance state.
In applications where the bus master may be in a state where all inputs/outputs are high
impedance at the same time (for example, if the bus master is reset during the transmission
of an instruction), the clock line (C) must be connected to an external pull-down resistor so
that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is
pulled low): this ensures that C does not become high at the same time as S goes low, and
so, that the tSLCH requirement is met. The typical value of R is 100 k.
Figure 3. Bus master and memory devices on the serial bus
R
SDO
SDI
SCK
Bus master
CS3 CS2 CS1
R
CQD
VCC
VSS
M93xxx
memory device
R
S ORG
VSS
VCC
CQD
VCC
VSS
M93xxx
memory device
R
C Q D VCC
VSS
M93xxx
memory device
S ORG
S ORG
AI14377b
8/33 DocID4997 Rev 15







M93C76-x equivalent, schematic
Instructions
M93C86-x M93C76-R M93C66-x M93C56-x M93C46-x
5.2.4
Erase Byte or Word
The Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or
word) to 1. Once the address has been correctly decoded, the falling edge of the Chip
Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be
detected by monitoring the READY/BUSY line, as described in Section 6: READY/BUSY
status.
Figure 7. ERASE, ERAL sequences
ERASE
S
D
1 1 1 An A0
CHECK
STATUS
Q
ERASE
ALL
S
D
ADDR
OP
CODE
BUSY
READY
1 0 0 1 0 Xn X0
CHECK
STATUS
5.2.5
Q
ADDR
OP
CODE
BUSY
READY
1. For the meanings of An and Xn, please see Table 4, Table 5 and Table 6.
AI00879B
Erase All
The Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set
to 1). The format of the instruction requires that a dummy address be provided. The Erase
cycle is conducted in the same way as the Erase instruction (ERASE). The completion of
the cycle can be detected by monitoring the READY/BUSY line, as described in Section 6:
READY/BUSY status.
16/33
DocID4997 Rev 15










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