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PDF ( 数据手册 , 数据表 ) CY14B116L

零件编号 CY14B116L
描述 16-Mbit (2048 K x 8/1024 K x 16/512 K x 32) nvSRAM
制造商 Cypress Semiconductor
LOGO Cypress Semiconductor LOGO 


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CY14B116L 数据手册, 描述, 功能
PRELIMINARY
CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
16-Mbit (2048 K × 8/1024 K × 16/512 K × 32)
nvSRAM
Features
16-Mbit nonvolatile static random access memory (nvSRAM)
25-ns, 30-ns and 45-ns access times
Internally organized as 2048 K × 8 (CY14X116L),
1024 K × 16 (CY14X116N), 512 K × 32 (CY14X116S)
Hands-off automatic STORE on power-down with only a
small capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
Sleep mode operation
Low power consumption
Active current of 75 mA at 45 ns
Standby mode current of 650 A
Sleep mode current of 10 A
Operating voltages:
CY14B116X: VCC = 2.7 V to 3.6 V
CY14E116X: VCC = 4.5 V to 5.5 V
Industrial temperature: –40 C to +85 C
Packages
44-pin thin small-outline package (TSOP II)
48-pin thin small-outline package (TSOP I)
54-pin thin small-outline package (TSOP II)
165-ball fine-pitch ball grid array (FBGA) package
Restriction of hazardous substances (RoHS) compliant
Offered speeds
44-pin TSOP II: 25 ns and 45 ns
48-pin TSOP I: 30 ns and 45 ns
54-pin TSOP II: 25 ns and 45 ns
165-ball FBGA: 25 ns and 45 ns
Functional Description
The C ypress CY14X1 16L/CY14X116N/CY14X116S i s a fast
SRAM, with a no nvolatile el ement in each memory cel l. T he
memory is organized as 2048 K bytes of 8 bits each or 1024 K
words of 16 bits each o r 512 K words of 32 bit s each . T he
embedded non volatile elemen ts inco rporate Qu antumTrap
technology, prod ucing the world’s mo st reli able nonvolatile
memory. The SRAM can be read and written an infinite number
of times. The nonvolatile d ata residin g in the nonvolatile
elements do not change when data is written to the SRAM. Data
transfers from th e SRAM to the nonvolatile e lements (the
STORE operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from th e non volatile me mory. Both th e ST ORE an d RECALL
operations are also available under software control.
Errata: The engineering samples do not meet the address hold after end of write (tHA) and static discharge voltage specifications. For information on silicon errata, see
Errata on page 33. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-67793 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 1, 2014http://www.Datasheet4U.com







CY14B116L pdf, 数据表
PRELIMINARY CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
Device Operation
The CY14X116L/CY14X116N/CY14X116S nvSRAM is made up
of two fu nctional components paired in the same physical cell.
These are a n SRAM memory cel l an d a n onvolatile
QuantumTrap cell. Th e SRAM memory cell operates as a
standard fast static RAM. Data in the SRAM is transferred to the
nonvolatile cel l (the STORE opera tion) automatical ly at
power-down, or from the n onvolatile cel l to th e SRAM (the
RECALL operation) on power-up. Both the STORE and RECALL
operations are also available under software control. Using this
unique architecture, all cells are stored and recalled in parallel.
During th e STORE and RECALL operations, SRAM read and
write operations are inh ibited. T he CY14 X116L/CY14X116N/
CY14X116S supports infinite reads and writes to the SRAM. In
addition, it provides infinite RECALL operations from the nonvol-
atile cells and up to 1 million STORE operations. See the Truth
Table For SRAM Operatio ns on p age 24 for a complete
description of read and write modes.
SRAM Read
The CY14X1 16L/CY14X116N/CY14X116S performs a read
cycle whenever CE and OE are LOW, and WE, ZZ, and HSB are
HIGH. T he a ddress spe cified o n pin s A 0–A20 or A 0–A19 or
A0–A18 determines which of the 2,097,152 d ata bytes o r
1,048,576 words of 16 bits or 524,288 words of 32 bits each are
accessed. Byte enables (BLE, BHE) determine which bytes are
enabled to the o utput, i n the case of 16-bit words and byte
enables (BA, BB, BC, BD) determine which bytes are enabled to
the output, in the case of 32-bit words. When the read is initiated
by an address transition, the outputs are valid after a delay of tAA
(read cycle 1) . If the read is initiated by CE or OE, the ou tputs
are valid at tACE or at tDOE, whichever is later (read cycle 2). The
data output repeatedly responds to address changes within the
tAA access ti me without the ne ed for transitions on any control
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycl e. The dat a on the common I/O pins
DQ0–DQ31 is written into the memory if it is valid tSD before the
end of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BLE, BHE determine which bytes
are written, in the case of 16-bit words and Byte Enable inputs
(BA, BB, BC, BD) determine which bytes are written, in the case
of 32-bit words. Keep OE HIGH during the entire write cycle to
avoid data bus contention on the common I/O lines. If OE is left
LOW, the internal circuitry turns off the output buffers tHZWE after
WE goes LOW.
AutoStore Operation (Power-Down)
The CY14 X116L/CY14X116N/CY14X116S stores d ata to the
nonvolatile QuantumTrap cells using one of the three storage
operations. These three operations are: Hardware STORE,
activated by the HSB; Software STORE, activated by an address
sequence; AutoS tore, on de vice p ower-down. T he AutoStore
operation i s a u nique fea ture of n vSRAM and is en abled b y
default on the CY14X116L/CY14X116N/CY14X116S.
During normal operation, the device draws current from VCC to
charge a ca pacitor conne cted to th e VCAP pi n. This stored
charge is used by the chip to perform a STORE operation during
power-down. If the voltage on the VCC pin drops below VSWITCH,
the part automatically disconnects the VCAP pin from VCC and a
STORE operation is i nitiated with power provided by the V CAP
capacitor.
Note If the capacitor is not connected to the VCAP pin, AutoStore
must be disabled using the soft sequence specified in the section
Preventing AutoStore on page 12. If AutoStore is enabled without
a capacitor on the V CAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the STORE. This
corrupts the data stored in the nvSRAM.
Figure 7. AutoStore Mode
VCC
VCC
0.1 uF
WE VCAP
VSS
VCAP
Figure 7 shows the proper connection of the storage capacitor
(VCAP) fo r the automatic STORE op eration. R efer to DC
Electrical Characteristics on page 13 for the size of the VCAP. The
voltage on the VCAP pin is driven to VVCAP by a regulator on the
chip. A pull-up resistor should be placed on WE to hold it inactive
during power-up. This pull-up resistor is only effective if the WE
signal is in trist ate during power-up. When the nvSRAM comes
out of po wer-up-RECALL, the h ost microcontroll er must be
active or the WE held i nactive u ntil the ho st microcontroller
comes out of reset.
To reduce unne cessary non volatile ST OREs, AutoS tore and
Hardware ST ORE operations a re ign ored unl ess at le ast one
write operation has taken place (which sets a write latch) since
the most recent ST ORE or RECALL cycle. Sof tware initiated
STORE cycl es are pe rformed re gardless of whether a write
operation has taken place.
Document #: 001-67793 Rev. *G
Page 8 of 38







CY14B116L equivalent, schematic
PRELIMINARY CY14B116L/CY14B116N/CY14B116S
CY14E116L/CY14E116N/CY14E116S
AC Switching Characteristics
Over the Operating Range[20]
Parameters
Cypress Parameter Alt Parameter
SRAM Read Cycle
tACE
tRC [22]
tAA [23]
tDOE
tOHA[23]
tLZCE[24]
tHZCE [21, 24]
tLZOE [24]
tHZOE [21, 24]
tPU [24]
tPD [24]
tDBE
tLZBE[24]
tHZBE[21, 24]
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
SRAM Write Cycle
tWC
tPWE
tSCE
tSD
tHD
tAW
tSA
tHA[25]
tHZWE [21, 24, 26]
tLZWE [24]
tBW
tWC
tWP
tCW
tDW
tDH
tAW
tAS
tWR
tWZ
tOW
Description
Chip enable access time
Read cycle time
Address access time
Output enable to data valid
Output hold after address change
Chip enable to output active
Chip disable to output inactive
Output enable to output active
Output disable to output inactive
Chip enable to power active
Chip disable to power standby
Byte enable to data valid
Byte enable to output active
Byte disable to output inactive
Write cycle time
Write pulse width
Chip enable to end of write
Data setup to end of write
Data hold after end of write
Address setup to end of write
Address setup to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
Byte enable to end of write
25 ns
Min Max
– 25
25 –
– 25
– 12
3–
3–
– 10
0–
– 10
0–
– 25
– 12
0–
– 10
25 –
20 –
20 –
10 –
0–
20 –
0–
0–
– 10
3–
20 –
30 ns
Min Max
– 30
30 –
– 30
– 14
3–
3–
– 12
0–
– 12
0–
– 30
– 14
0–
– 12
30 –
24 –
24 –
14 –
0–
24 –
0–
0–
– 12
3–
24 –
45 ns
Unit
Min Max
– 45 ns
45 - ns
– 45 ns
– 20 ns
3 – ns
3 – ns
– 15 ns
0 – ns
– 15 ns
0 – ns
– 45 ns
– 20 ns
0 – ns
– 15 ns
45 – ns
30 – ns
30 – ns
15 – ns
0 – ns
30 – ns
0 – ns
0 – ns
- 15 ns
3 – ns
30 – ns
Notes
20. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 toVCC(Typ), and output loading of the specified
IOL/IOH and 30 pF load capacitance as shown in Figure 9.
21. tHZCE, tHZOE, tHZBE and tHZWE are specified with a load capacitance of 5 pF. Transition is measured ±200 mV from the steady state output voltage.
22. WE must be HIGH during SRAM read cycles.
23. Device is continuously selected with CE, OE and BLE, BHE/BA, BB, BC, BD LOW.
24. These parameters are only guaranteed by design and are not tested.
25. Errata: The engineering samples do not meet the address hold after end of write (tHA) specification of > 0 ns. The current silicon meets tHA > 2 ns. For more information,
see Errata on page 33.
26. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
Document #: 001-67793 Rev. *G
Page 16 of 38










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