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PDF ( 数据手册 , 数据表 ) GP-MF802

零件编号 GP-MF802
描述 Industrial Camera Service Manual
制造商 Panasonic
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GP-MF802 数据手册, 描述, 功能
ORDER NO. AVS9705028C1
D0
Industrial Camera
GP-MF802
Camera Cable : Option
Lens :
Option
SPECIFICATIONS
Pick-up Device :
Image Size :
Synchronization :
External Reset :
Horizontal Resolution :
Minimum Illumination :
Signal to Noise Ratio :
Electronic Shutter :
Lens Mount :
Vibration Resistance :
Shock Resistance :
Power Source :
Ambient Temperature :
Progressive Scanning Interline Transfer CCD with 659 (H) x 494 (V) pixels.
1/3” (6.3 (H) x 6.4 (V) mm)
2 : 1 interlace 1-line interlace (Frame accumulation)
2 : 1 interlace 2-line interlace (Field accumulation)
2-line sequential (at non-interlaced external HD/VD)
internal or external (Selectable automatically)
Internal : Built-in sync generator
External : 4.0 V[p-p] / 75 Horizontal drive and vertical drive pulses for 2 : 1 interlace or sequential
scanning
External signal (4.0 V[p-p]/75 , negative) supplied to EXT VD IN connector can be used as reset sig -
nal
480 lines at center
6.5 lx (0.65 footcandles ) at F1.4, (Manual Gain Max, γ ON, 2 : 1 interlace, without shutter)
56 dB Typical (Fix Gain, γ OFF, 2:1 interlace without shutter)
7-step (1/100 to 1/8,000) at normal.
4-step (1/2,000 to 1/16,000) at Shutter Trigger-A.
Approx. 1/2,000 at Shutter Trigger-B.
C-mount
8 G (10 Hz - 150 Hz), (2 hours each for three axes)(IEC 68)
80 G (IEC 68) *IEC=International Electrotechnical Commission
12V DC, 190 mA
10˚C - +50˚C (14˚F - 122˚F)
C1997 Matsushita Communication Industrial Co., Ltd.
All rights reserved. Unauthorized copying and
R distribution is a violation of law.
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GP-MF802 pdf, 数据表
CIRCUIT DESCRIPTION
IC Description
1. Drive Board
1.1. IC5 on the Drive Board is using the CCD Drive Pulse Generator IC YWBU121070A.
Description of this IC is as follows:
VD 49
PBLK 50
CSYNC 51
CBLK 52
HHG1_A 53
HHG1_B 54
HHG2 55
VDD 56
GND 57
EXVD 58
EXHD 59
V1 60
V2 61
V3 62
V4 63
VDD 64
(TOP VIEW)
32 VDD
31 ADCLK
30 DS2
29 DS1
28 VDD
27 STON
26 HRPH
25 R
24 GND
23 RWO
22 RWI
21 VDD
20 H2
19 GND
18 H1
17 VDD
Pin Name
1 GND
2 SUB
3 CH1
4 TEST
5 SG
6 TEST1
7 XO2
8 XI2
9 GND
10 PCO
11 VDD
12 XI1
13 XO1
14 TEST2
15 HRPO
16 GND
17 VDD
18 H1
19 GND
20 H2
21 VDD
22 RWI
23 RWO
24 GND
25 R
26 HRPH
27 STON
28 VDD
I/O Description
– Ground terminal.
O Electronic Shutter Pulse output terminal.
O Charge Pulse output terminal for ΦV1.
I Test mode switching terminal.
O Sensor Gate Pulse output terminal.
I Test signal input terminal.
O
Crystal Oscillator 2 connecting terminals.
I
– Ground terminal.
O Phase Comparator output terminal.
– Power supply terminal.
I
Crystal Oscillator 1 connecting terminals.
O
I Test signal input terminal.
I HRPO signal input terminal.
– Ground terminal.
– Power supply terminal.
O ΦH1 Transfer Pulse output terminal.
– Ground terminal.
O ΦH2 Transfer Pulse output terminal.
– Power supply terminal.
I Reset Pulse Width Adjust signal input
terminal.
O Reset Pulse Width Adjust signal output
terminal.
– Ground terminal.
O Reset Pulse output terminal.
I HRPH signal input terminal.
I STON signal input terminal.
– Power supply terminal.
Pin Name I/O
Description
29 DS1
30 DS2
O CDS Sample Hold Pulse output
O terminals.
31 ADCLK O AD Clock Pulse output terminal.
32 VDD
– Power supply terminal.
33 GND
– Ground terminal.
34 TEST3
35 TEST4
I Test signal input terminals.
I
36 DRV1
37 DRV2
I DRV signal input terminals.
I
38 VMD1 I
39 VMD2 I VMD signal input terminals.
40 VMD3 I
41 VDD
– Power supply terminal.
42 MS
I MS signal input terminal.
43 CPOB O OB (Optical Black) Clamp Pulse output
terminal.
44 CP2
O
45 CP3
O Clamp Pulse output terminals.
46 CP4
O
47 HD
O Horizontal Drive signal output terminal.
48 GND
– Ground terminal.
49 VD
O Vertical Drive signal output terminal.
50 PBLK O Pre Blanking Pulse output terminal.
51 CSYNC O Composite Sync signal output terminal.
52 CBLK O Composite Blanking Pulse output terminal.
53 HHG1_A O HHG1_A signal output terminal.
54 HHG1_B O HHG1_B signal output terminal.
55 HHG2 O HHG2 signal output terminal.
56 VDD
– Power supply terminal.
57 GND
– Ground terminal.
58 EXVD I External VD signal input terminal.
59 EXHD I External HD signal input terminal.
60 V1
O ΦV1 Transfer Pulse output terminal.
61 V2
O ΦV2 Transfer Pulse output terminal.
62 V3
O ΦV3 Transfer Pulse output terminal.
63 V4
O ΦV4 Transfer Pulse output terminal.
64 VDD
– Power supply terminal.
5







GP-MF802 equivalent, schematic
Connect the terminated Oscilloscope with 75to Video 2
of the Camera Cable.
Set the Switch 1 and Switch 2 to OFF position.
Adjust VR4 so that the Pedestal signal level becomes
same as that of the Video 1 as shown in Fig. 5-7.
Same level
as Video 1
Fig. 5-7
Remove the Cap from the Lens, and connect the
Oscilloscope to TP1 on the Sensor Board.
Adjust the Lens Iris so that the CCD output signal at TP1
becomes 214 mV.
Adjust VR5 so that the Video signal level becomes 100
IRE (714 mV) as shown in Fig.5-8, and confirm that the
Sync signal level is 40 ± 4.2 IRE (286 ± 30 mV) as shown
in Fig. 5-8.
100 IRE
(714 mV)
40 ± 4.2 IRE
(286 ± 30 mV)
Fig. 5-8
Set the Switch 1 to ON position.
Confirm that both Pedestal signal level and Video signal
level are within specification.
Set the Switch 1 to OFF position.
(6). VSUB Fine Adjustment
Adjust:
VR6 (Vsub1)
Drive Board
VR7 (Vsub2)
Drive Board
Observe Video Monitor
Aim the Camera at the 40-watt Lamp placed in the dark
background.
Set the Lens Iris fully open ( F1.4).
If the blooming and noise appear on the Video Monitor as
shown in Fig. 5-9, readjust VR7.
Notes: VR7 should be adjusted to the point where the
blooming just eliminates.
Do not turn VR7 too much.
If readjust VR7, must be readjusted from the
adjustment steps (3) through (5).
Set the Switch 1 to ON position, and confirm that the no
blooming appears on the Video Monitor.
Set the Switch 1 to OFF position.
Set the Switch 2 to ON position.
If the blooming and noise appear on the Video Monitor as
shown in Fig. 5-9, readjust VR6.
Notes: VR6 should be adjusted to the point where the
blooming just eliminates.
Do not turn VR6 too much.
If readjust VR6, must be readjusted from the
adjustment steps (3) through (5).
No Good
Fig. 5-9
Good
13










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