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PDF ( 数据手册 , 数据表 ) NB3L853141

零件编号 NB3L853141
描述 2.5V/3.3V 1:5 LVPECL Fanout Buffer
制造商 ON Semiconductor
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NB3L853141 数据手册, 描述, 功能
NB3L853141
2.5V/3.3V 1:5 LVPECL
Fanout Buffer
Description
The NB3L853141 is a low skew 1:5 LVPECL Clock fanout buffer
designed explicitly for low output skew applications.
The NB3L853141 features a multiplexed input which can be driven
by either a differential or single−ended input to allow for the
distribution of a lower speed clock along with the high speed system
clock.
The SEL pin will select the differential clock inputs, CLK0 &
CLK0, when LOW (or left open and pulled LOW by the internal
pull−down resistor). When SEL is HIGH, the single−ended CLK1
input is selected.
The common enable (EN) is synchronous so that the outputs will
only be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore, all associated specification limits are referenced to the
negative edge of the clock input.
Features
700 MHz Maximum Clock Output Frequency
CLK0 and CLK0 can Accept Differential LVPECL, LVDS, HCSL,
LVHSTL, SSTL, LVCMOS
CLK1 can Accept LVCMOS and LVTTL
Five Differential LVPECL Clock Outputs
1.5 ns Maximum Propagation Delay
Operating Range: VCC = 2.375 V to 3.8 V
LVCMOS Compatible Control Inputs
Selectable Differential or LVCMOS Clock Inputs
Synchronous Clock Enable
30 ps Max. Skew Between Outputs
−40°C to +85°C Ambient Operating Temperature Range
TSSOP−20 Package
These are Pb−Free Devices
Applications
Computing and Telecom
Routers, Servers and Switches
Backplanes
www.onsemi.com
MARKING
DIAGRAM
TSSOP−20
DT SUFFIX
CASE 948E
NB3L
3141
ALYW
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
EN
CLK0
CLK0
+
CLK1
SEL
0
1
D
Q
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Figure 1. Simplified Logic Diagram of
NB3L853141
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. 2
1
Publication Order Number:
NB3L853141/D







NB3L853141 pdf, 数据表
NB3L853141
Driver
Device
Q
Q
Zo = 50 W
Zo = 50 W
50 W
50 W
D
Receiver
Device
D
VTT
VTT = VCC − 2.0 V
Figure 10. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device
NB3L853141DTG
Package
TSSOP−20
(Pb−Free)
Shipping
75 Units / Rail
NB3L853141DTR2G
TSSOP−20
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
8














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