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PDF ( 数据手册 , 数据表 ) H6850P

零件编号 H6850P
描述 Novel Low Cost Green-Power PWM Controller
制造商 Hi-Sincerity
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H6850P 数据手册, 描述, 功能
HI-SINCERITY
MICROELECTRONICS CORP.
Spec. No. : IC200912
Issued Date : 2009.07.15
Revised Date :
Page No. : 1/13
H6850 Series
Novel Low Cost Green-Power PWM Controller
With Low EMI Technique
Feature
z Low Cost, PWM&PFM&CRM (Cycle
Reset Mode)
z Low Start-up Current (about 3μA)
z Low Operating Current (about 1.2mA)
z Current Mode Operation
z Under Voltage Lockout (UVLO)
z Built-in Synchronized Slope
Compensation
z Built-in Low EMI Technique
z Programmable PWM Frequency
z Audio Noise Free Operation
z Leading edge Blanking on Sense input
z Constant output power limiting for
universal AC input Range
z SOT-23-6 L SOP8 and DIP-8 Pb-Free
Packaging
z Good Protection Coverage With Auto
Self-Recovery
z Compatible with SG6848 (6849) /
SG5701/SG5848/LD7535 (7550) /
OB2262 (2263)/OB22782279
z Complete Protection with
¾ Soft Clamped GATE output voltage
18.0V
¾ VDD over voltage protect 34.0V
¾ Cycle-by-cycle current limiting
¾ Output SCP (Short circuit Protection)
¾ Output OLP (Over Load Protection)
¾ High-Voltage CMOS Process with ESD
Applications
z Switching AC/DC Adaptor
z Battery Charger
z Open Frame Switching Power Supply
z Standby Power Supplies
z Set-Top Box Power Supplies
z 384X Replacement
General Description
The H68 50 is a highly integrated low cost
current mode PWM controller, which is ideal
for small power cur rent mode of of fline
AC-DC fly- back converter applic ations.
Making use of external resistors, the IC
changes the operating frequency and
automatically enters the PFM/CRM ( Cycle
Reset Mode) und er light-load/zer o-load
conditions. This can minimize standby
power consumption and achieve powe r-
saving functions. With a very lo w st art-up
current, the H685 0 could use a large value
start-up resistor (2M).
Built-in synchronized slo pe compens ation
enhances the st ability of the syste m and
avoids sub-harmonic oscillation. D ynamic
peak current limiting circuit minimizes output
power chang e caused by delay time of the
system over a universal AC input range.
Leading edge blanking circuit on current
sense input could remove the signal glitch
due to snubber circuit diode reverse
recovery and thus greatly reduces the
external component count and system cost
in the design. Cycle-by-Cycle current
limiting ensures safe operation even during
short-circuit.
Excellent EMI performance is achieved
built-in soft driver and low EMI technique.
The H68 50 offers perfect protection like
OVP(Over Voltage Prote ction)OLP(Over
Load Protection) SCP(Short circuit
protection)OTPSense Fault Protection
and OCP(Over current protection). The
H6850’s output driver is soft clamped to
maximum 18.0V to protect the power
MOSFET. H6850 is offered in SOT-23-6L,
SOT-8 and DIP-8 packages.
H6850P, H6850S,H6850NF
HSMC Product Specification
http://www.Datasheet4U.com







H6850P pdf, 数据表
HI-SINCERITY
MICROELECTRONICS CORP.
Spec. No. : IC200804
Issued Date : 2008.09.19
Revised Date :
Page No. : 8/13
starts, the delay time is set. When the RI
resistance is 100Kohm , the delay time
TOLP&SCP is between 33m S and 50mS. The
relationship between RI and T OLP&SCP
follows the below equation.
RI × 2
6 ×103
(mS )
< TOLP&SCP
<
RI × 3
6 ×103
(mS )
Anti Intermission Surge
When the p ower suppli es change the
heavy loa d to light load i mmediately, there
could be tow phenomena caused by system
delay. They are output voltage overshot and
intermission surge. To avoid it, the anti
intermission surge is built in the H6850. If it
occurs, the FB current is to increase rapidly,
the GATE would be cut off for a while, VDD
pin voltage descends gradually. When VDD
reaches 9.4V, the GATE pin would operate
again, which the frequency is 22KHz.
Leading-edge Blanking (LEB)
Each time the power MOSFET is
switched on, a turn-on spike will inevitably
occur at the Sense pin, which would disturb
the internal signal from the sampling of the
RSENSE. There is a 300nS leading edge
blanking time built in to avoid the effect of
the turn-on spike, and the power MOSFET
cannot be switched off during the moment.
So that the conventional external RC
filtering on sense input is no longer required.
Over Voltage Protection (OVP)
There is a 34V over-voltage protection
circuit in the H6850 to improve the credibility
and extend the life of the chip. When the
VDD voltage is over 34V, the GATE pin is to
shutdown immediately and the VDD voltage
is to descend rapidly.
GATE Driver & Soft Clamped
The H6850’ output designs a totem pole
to drive a periphery power MOSFET. The
dead time is introduced to minimize the
transfixion current during the output
operating. The novel soft clamp technology
is introduced to protect the periphery power
MOSFET from breaking down and current
saturation of the Zener.
Low EMI technique
The frequen cy low EMI technique is
introduced in the H6850. As following figure,
the internal oscillatio n frequency is
modulated b y itself. A whole surg e cycle
includes 128 pulses and the jittering r anges
from -4% to +4%. Thus, the function could
minimize the electromagnetic interferer from
the power supply module.
Frequency(HZ)
70K
65K
H6850
60K
Time
Frequency low EMI
H6850P, H6850S,H6850NF
HSMC Product Specification














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