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PDF ( 数据手册 , 数据表 ) ADV7513

零件编号 ADV7513
描述 Low-Power HDMI 1.4A Compatible Transmitter PROGRAMMING GUIDE
制造商 Analog Devices
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ADV7513 数据手册, 描述, 功能
ADV7513
Low-Power HDMI 1.4A Compatible Transmitter
PROGRAMMING
GUIDE
- Revision B–
March 2012
http://www.Datasheet4U.com







ADV7513 pdf, 数据表
PROGRAMMING GUIDE
ADV7513
TABLE OF TABLES
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
I2C Bus Related Registers (Main Map)............................................................................................................................................................................. 15
Hot Plug Detect (HPD) and Monitor Sense Related Registers (Main Map) ............................................................................................................... 17
Hot Plug Detect (HPD) and Monitor Sense Related Registers (CEC Map)................................................................................................................ 18
HDMI DVI Selection Related Registers (Main Map)..................................................................................................................................................... 18
AV Mute Related Registers (Main Map)........................................................................................................................................................................... 19
TMDS Power-Down Related Registers (Main Map) ...................................................................................................................................................... 20
Source Product Description (SPD) Packet Related Registers (Main Map) ................................................................................................................. 22
Source Product Description (SPD) Packet Related Registers (Packetmemory Map) ................................................................................................ 22
Spare Packets Related Registers (Main Map)................................................................................................................................................................... 23
Spare Packets Related Registers (Packetmemory Map) .............................................................................................................................................. 23
DDCController Status ..................................................................................................................................................................................................... 24
Error Code Definitions.................................................................................................................................................................................................... 24
System Monitoring Related Registers (Main Map)...................................................................................................................................................... 25
Fixed Registers That Must Be Set (Main Map) ............................................................................................................................................................ 25
Input ID Selection ............................................................................................................................................................................................................ 26
Normal RGB or YCbCr 4:4:4 (24 bits) with Separate Syncs; Input ID = 0............................................................................................................... 27
YCbCr 4:2:2 Formats (24, 20, or 16 bits) Input Data Mapping: R0x48[4:3] = ‘00’ (evenly distributed) Input ID = 1 or 2.............................. 28
YCbCr 4:2:2 Formats (12, 10, or 8 bits) Input Data Mapping: R0x48[4:3] = ‘00’ (evenly distributed) Input ID = 3, 4, 7, or 8....................... 29
YCbCr 4:2:2 (8 bits) DDR with Separate Syncs: Input ID = 6, right justified (R0x48[4:3] = ‘01’) ....................................................................... 30
YCbCr 4:2:2 (8 bits) DDR with Separate Syncs: Input ID = 6, left justified (R0x48[4:3] = ‘10’) .......................................................................... 30
YCbCr 4:2:2 (12, 10, 8 bits) DDR with Separate Syncs: Input ID = 6, evenly distributed (R0x48[4:3] = ‘00’) ................................................... 31
Input Formatting Related Registers (Main Map)......................................................................................................................................................... 34
Video Mode Detection Related Registers (Main Map) ............................................................................................................................................... 37
Pixel Repetition Related Registers (Main Map) ........................................................................................................................................................... 41
DE and HSync/Vsync Generation Common Format Settings .................................................................................................................................. 48
Register Settings for DE Generation.............................................................................................................................................................................. 48
Register Settings for Sync Adjustment .......................................................................................................................................................................... 48
Register Settings for Embedded Sync Processing ........................................................................................................................................................ 49
DE, Hsync and Vsync Generation Related Registers (Main Map)............................................................................................................................ 49
CSC Mode Settings........................................................................................................................................................................................................... 52
CSC Port Mapping ........................................................................................................................................................................................................... 53
HDTV YCbCr (Limited Range) to RGB (Limited Range) ......................................................................................................................................... 53
HDTV YCbCr (Limited Range) to RGB (Full Range) ................................................................................................................................................ 53
SDTV YCbCr (Limited Range) to RGB (Limted Range)............................................................................................................................................ 53
SDTV YCbCr (Limited Range) to RGB (Full Range) ................................................................................................................................................. 53
RGB (Limited Range) to HDTV YCbCr (Limited Range) ......................................................................................................................................... 54
Page 8 of 188
Rev. B







ADV7513 equivalent, schematic
PROGRAMMING GUIDE
ADV7513
4.2 General Control
4.2.1
Hot Plug Detect (HPD) and Monitor Sense
To operate the ADV7513, it is necessary to monitor the Hot Plug Detect (HPD) signal and power up the part after HPD
becomes high. To power up the part, the Power Down register bit (0x41[6]) must be written to 0 when the HPD pin is high.
The status of the HPD pin can be read in register bit 0x42[6]. Both the HPD pin and Capability Discovery and Control (CDC)
HPD will be used for the internal HDCP signal. The CDC HPD signal is used as the HPD signal when HEC is active, because
the physical HPD line needs to be held high for HEC. The HPD source can be selected with the HPD Control Register Bits
0xD6[7:6]. When these bits are set to 0b00, both the HPD pin and CDC HPD will be used for the internal HPD signal. When
these bits are set to0b01 only the CDC HPD will be used, and 0b10 means that only the HPD pin will be used. When
0xD6[7:6] is set to 0b11 the HPD signal will always be high, but the HPD interrupt will still respond to the HPD pin. To use
the CDC HPD register bit 0x7F[6] of the CEC Map must be set to 1 and 0x80 and 0x81of the CEC Map need to be set to
products containing the HDMI Tx’s physical address.
When the signal on HPD is low, some registers cannot be written to. When HPD goes from high to low, some registers will be
reset to their defaults. For additional details see ▶ Table 74. Refer to ▶ 4.10 for details on the use of interrupts.
If there is a need to power up the part when the HPD signal is low, the HPD can be overridden using the HPD Control
register bit (0xD6[7] = 1. This would be needed, for example, when reading the EDID from an HDMI port when the HPD is
low in order to find its CEC physical address.
The best method to determine when the HPD is high is to use the interrupt system. The bit representing an HPD interrupt is
0x96[7]. Refer to ▶ 4.10 for details on the use of interrupts.
Monitor Sense refers to the detection of TMDS clock line pull-ups in the HDMI sink. If greater than 1.8V is detected, the
Monitor Sense interrupt will be triggered and the Monitor Sense State bit (0x42[5]) will be 1.
One reason to detect the Monitor Sense is to delay powering up the chip until the Rx is actually ready to receive signals. A
typical implementation for a sink is to tie the HDMI 5V to HPD through a series resistor. In this case, the HPD signal will be
detected regardless of whether the sink is powered on and ready to receive audio and video. For this reason it is best to wait
for both the Monitor Sense and HPD before powering up the chip when trying to achieve minimum power consumption.
Page 16 of 188
Rev. B










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