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PDF ( 数据手册 , 数据表 ) F25L32QA-50HG2S

零件编号 F25L32QA-50HG2S
描述 32 Mbit Serial Flash Memory
制造商 ESMT
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F25L32QA-50HG2S 数据手册, 描述, 功能
ESMT
Flash
„ FEATURES
y Single supply voltage 2.65~3.6V
y Standard, Dual and Quad SPI
y Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz / 86MHz / 104MHz
- Fast Read Dual/Quad max frequency: 50MHz / 86MHz /
104MHz
(100MHz / 172MHz / 208MHz equivalent Dual SPI;
200MHz / 344MHz / 416MHz equivalent Quad SPI)
y Low power consumption
- Active current: 25 mA (max.)
- Standby current: 30 μ A (max.)
- Deep Power Down current: 10 μ A (max.)
y Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y Program
- Page programming time: 1.5 ms (typical)
F25L32QA (2S)
32 Mbit Serial Flash Memory
with Dual and Quad
y Erase
- Chip Erase time 10 sec (typical)
- 64K bytes Block Erase time 1 sec (typical)
- 32K bytes Block Erase time 500 ms (typical)
- 4K bytes Sector Erase time 120 ms (typical)
y Page Programming
- 256 byte per programmable page
y Program / Erase Suspend
y Lockable 512 bytes OTP security sector
y SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y End of program or erase detection
y Write Protect ( WP )
y Hold Pin ( HOLD )
y All Pb-free products are RoHS-Compliant
„ ORDERING INFORMATION
Product ID
Speed
F25L32QA –50PAG2S 50MHz
F25L32QA –86PAG2S 86MHz
F25L32QA –100PAG2S 104MHz
F25L32QA –50PHG2S 50MHz
F25L32QA –86PHG2S 86MHz
F25L32QA –100PHG2S 104MHz
F25L32QA –50HG2S 50MHz
F25L32QA –86HG2S 86MHz
F25L32QA –100HG2S 104MHz
Package
Comments
8-lead
SOIC
200 mil
Pb-free
16-lead
SOIC
300 mil
Pb-free
8-contact
WSON
6x5 mm
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2012
Revision: 1.3
1/50
Free Datasheet http://www.Datasheet4U.com







F25L32QA-50HG2S pdf, 数据表
ESMT
F25L32QA (2S)
64KB
Block
43
42
41
40
39
38
37
Table 1: Sector Address Table – Continued III
32KB
Block
87
86
85
84
83
82
81
80
79
78
77
76
75
74
Sector
703
:
696
695
:
688
687
:
680
679
:
672
671
:
664
663
:
656
655
:
648
647
:
640
639
:
632
631
:
624
623
:
616
615
:
608
607
:
600
599
:
592
Sector Size
(Kbytes)
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
Address range
2BF000H – 2BFFFFH
:
2B8000H – 2B8FFFH
2B7000H – 2B7FFFH
:
2B0000H – 2B0FFFH
2AF000H – 2AFFFFH
:
2A8000H – 2A8FFFH
2A7000H – 2A7FFFH
:
2A0000H – 2A0FFFH
29F000H – 29FFFFH
:
298000H – 298FFFH
297000H – 297FFFH
:
290000H – 290FFFH
28F000H – 28FFFFH
:
288000H – 288FFFH
287000H – 287FFFH
:
280000H – 280FFFH
27F000H – 27FFFFH
:
278000H – 278FFFH
277000H – 277FFFH
:
270000H – 270FFFH
26F000H – 26FFFFH
:
268000H – 268FFFH
267000H – 267FFFH
:
260000H – 260FFFH
25F000H – 25FFFFH
:
258000H – 258FFFH
257000H – 257FFFH
:
250000H – 250FFFH
Block Address
A21 A20 A19 A18 A17 A16
101011
101010
101001
101000
100111
100110
100101
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2012
Revision: 1.3
8/50
Free Datasheet http://www.Datasheet4U.com







F25L32QA-50HG2S equivalent, schematic
ESMT
Protection Level
0
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
All Blocks
All Blocks
Bottom 32/64
Bottom 48/64
Bottom 56/64
Bottom 60/64
Bottom 62/64
Bottom 63/64
All Blocks
F25L32QA (2S)
Table 3: F25L32QA Block Protection Table
Status Register Bit
BP3 BP2 BP1 BP0
Protected Memory Area
64KB Block Range
Address Range
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
None
Block 63
Block 62~63
Block 60~63
Block 56~63
Block 48~63
Block 32~63
Block 0~63
Block 0~63
Block 0~31
Block 0~47
Block 0~55
Block 0~59
Block 0~61
Block 0~62
Block 0~63
None
3F0000H – 3FFFFFH
3E0000H – 3FFFFFH
3C0000H – 3FFFFFH
380000H – 3FFFFFH
300000H – 3FFFFFH
200000H – 3FFFFFH
000000H – 3FFFFFH
000000H – 3FFFFFH
000000H – 1FFFFFH
000000H – 2FFFFFH
000000H –37FFFFH
000000H – 3BFFFFH
000000H – 3DFFFFH
000000H – 3EFFFFH
000000H – 3FFFFFH
Block Protection (BP3, BP2, BP1, BP0)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
memory area, as defined in Table 3, to be software protected
against any memory Write (Program or Erase) operations. The
Write Status Register (WRSR) instruction is used to program the
BP3, BP2, BP1 and BP0 bits as long as WP is high or the
Block- Protection-Look (BPL) bit is 0. Chip Erase can only be
executed if BP3, BP2, BP1 and BP0 bits are all 0. After power-up,
BP3, BP2, BP1 and BP0 bits are set to 0.
Block Protection Lock-Down (BPL)
WP pin driven low (VIL), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1 and BP0 bits. When
the WP pin is driven high (VIH), the BPL bit has no effect and its
value is “Don’t Care”. After power-up, the BPL bit is reset to 0.
Quad Enable (QE)
When the Quad Enable bit is reset to “0” (factory default), WP
and HOLD pins are enabled. When QE pin is set to “1”, Quad
SIO2 and SIO3 are enabled. (The QE should never be set to “1”
during standard and Dual SPI operation if the WP and HOLD
pins are tied directly to the VDD or VSS.)
Program / Erase Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register
that is set to 1 after executing a Program / Erase Suspend (75H)
instruction.
The SUS Status bit is cleared to 0 by Program / Erase Resume
(7AH) instruction as well as a power-down, power-up cycle.
Elite Semiconductor Memory Technology Inc.
Publication Date: Sep. 2012
Revision: 1.3
16/50
Free Datasheet http://www.Datasheet4U.com










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