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PDF ( 数据手册 , 数据表 ) F25L32QA-86PHG

零件编号 F25L32QA-86PHG
描述 3V Only 32 Mbit Serial Flash Memory
制造商 ESMT
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F25L32QA-86PHG 数据手册, 描述, 功能
ESMT
Flash
„ FEATURES
y Single supply voltage 2.7~3.6V
y Standard, Dual and Quad SPI
y Speed
- Read max frequency: 33MHz
- Fast Read max frequency: 50MHz / 86MHz / 100MHz
- Fast Read Dual/Quad max frequency: 50MHz / 86MHz /
100MHz
(100MHz / 172MHz / 200MHz equivalent Dual SPI;
200MHz / 344MHz / 400MHz equivalent Quad SPI)
y Low power consumption
- Active current: 35 mA
- Standby current: 30 μ A
- Deep Power Down current: 5 μ A
y Reliability
- 100,000 typical program/erase cycles
- 20 years Data Retention
y Program
- Byte programming time: 7 μ s (typical)
- Page programming time: 1.5 ms (typical)
F25L32QA
3V Only 32 Mbit Serial Flash Memory
with Dual and Quad
y Erase
- Chip erase time 25 sec (typical)
- Block erase time 1 sec (typical)
- Sector erase time 90 ms (typical)
y Page Programming
- 256 byte per programmable page
y Lockable 512 bytes OTP security sector
y SPI Serial Interface
- SPI Compatible: Mode 0 and Mode 3
y End of program or erase detection
y Write Protect ( WP )
y Hold Pin ( HOLD )
y All Pb-free products are RoHS-Compliant
„ ORDERING INFORMATION
Product ID
Speed
Package
F25L32QA –50PAG
50MHz 8 lead SOIC 200mil
F25L32QA –86PAG
86MHz 8 lead SOIC 200mil
F25L32QA –100PAG 100MHz 8 lead SOIC 200mil
F25L32QA –50PHG
50MHz 16 lead SOIC 300mil
F25L32QA –86PHG
86MHz 16 lead SOIC 300mil
F25L32QA –100PHG 100MHz 16 lead SOIC 300mil
Comments
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
Pb-free
„ GENERAL DESCRIPTION
The F25L32QA is a 32Megabit, 3V only CMOS Serial Flash
memory device. The device supports the standard Serial
Peripheral Interface (SPI), and a Dual/Quad SPI. ESMT’s
memory devices reliably store memory data even after 100,000
programming and erase cycles.
The memory array can be organized into 16,384 programmable
pages of 256 byte each. 1 to 256 byte can be programmed at a
time with the Page Program instruction.
E„lite Semiconductor Memory Technology Inc.
The device features sector erase architecture. The memory array
is divided into 1024 uniform sectors with 4K byte each; 64
uniform blocks with 64K byte each. Sectors can be erased
individually without affecting the data in other sectors. Blocks can
be erased individually without affecting the data in other blocks.
Whole chip erase capabilities provide the flexibility to revise the
data in the device. The device has Sector, Block or Chip Erase
but no page erase.
The sector protect/unprotect feature disables both program and
erase operations in any combination of the sectors of the
memory.
Publication Date: Jan. 2010
Revision: 1.1
1/40
Free Datasheet http://www.Datasheet4U.com







F25L32QA-86PHG pdf, 数据表
ESMT
F25L32QA
Block
11
10
9
8
7
6
5
4
3
2
1
0
Table 1: F25L32QA Sector Address Table – Continued IV
Sector
191
:
176
175
:
160
159
:
144
143
:
128
127
:
112
111
:
96
95
:
80
79
:
64
63
:
48
47
:
32
31
:
16
15
:
0
Sector Size
(Kbytes)
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
4KB
:
4KB
Address range
Block Address
A21 A20 A19 A18 A17 A16
0BF000H – 0BFFFFH
: 001011
0B0000H – 0B0FFFH
0AF000H – 0AFFFFH
: 001010
0A0000H – 0A0FFFH
09F000H – 09FFFFH
: 001001
090000H – 090FFFH
08F000H – 08FFFFH
: 001000
080000H – 080FFFH
07F000H – 07FFFFH
: 000111
070000H – 070FFFH
06F000H – 06FFFFH
: 000110
060000H – 060FFFH
05F000H – 05FFFFH
: 000101
050000H – 050FFFH
04F000H – 04FFFFH
: 000100
040000H – 040FFFH
03F000H – 03FFFFH
: 000011
030000H – 030FFFH
02F000H – 02FFFFH
: 000010
020000H – 020FFFH
01F000H – 01FFFFH
: 000001
010000H – 010FFFH
00F000H – 00FFFFH
: 000000
000000H – 000FFFH
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2010
Revision: 1.1
8/40
Free Datasheet http://www.Datasheet4U.com







F25L32QA-86PHG equivalent, schematic
ESMT
F25L32QA
Fast Read Dual Output (50 MHz ~ 100 MHz)
The Fast Read Dual Output (3BH) instruction is similar to the
standard Fast Read (0BH) instruction except the data is output
on bidirectional I/O pins (SIO0 and SIO1). This allows data to be
transferred from the device at twice the rate of standard SPI
devices. This instruction is for quickly downloading code from
Flash to RAM upon power-up or for applications that cache code-
segments to RAM for execution.
The Fast Read Dual Output instruction is initiated by executing
an 8-bit command, 3BH, followed by address bits [A23 -A0] and a
dummy byte. CE must remain active low for the duration of the
Fast Read Dual Output cycle. See Figure 4 for the Fast Read
Dual Output sequence.
CE
MODE3
SCK MODE0
0 12 34 56 78
15 16 23 24
31 32 39 40
43 44
47 48
51 52
55 56
Dummy
IO0 switches from In put to Ouput
SIO0
SIO1
MSB
3B
ADD.
ADD.
MSB
HIGH IMPENANCE
ADD.
6420 6420 6420 64206 4
DOUT
DOUT
DOU T
DOU T
D OUT
N N+1 N+2 N+3 N+4
75317531 7531 753175
Note: The input data durin g the dummy clocks is “don’t care”.
However , the IO0 pin should be high-impefance piror to th e falling edge of the first data clock.
Figure 4: Fast Read Dual Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2010
Revision: 1.1
16/40
Free Datasheet http://www.Datasheet4U.com










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