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PDF ( 数据手册 , 数据表 ) C8051F59x

零件编号 C8051F59x
描述 Mixed Signal ISP Flash MCU Family
制造商 Silicon Laboratories
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C8051F59x 数据手册, 描述, 功能
Analog Peripherals
- 12-Bit ADC
Up to 200 ksps
Up to 32 external single-ended inputs
VREF from on-chip VREF, external pin or VDD
Internal or external start of conversion source
Built-in temperature sensor
- Three Comparators
Programmable hysteresis and response time
Configurable as interrupt or reset source
Low current
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
- Typical operating current: 15 mA at 50 MHz;
Typical stop mode current: 230 µA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
Automotive Qualified
- Temperature Range: –40 to +125 °C
C8051F58x/F59x
Mixed Signal ISP Flash MCU Family
Memory
- 8448 bytes internal data RAM (256 + 8192 XRAM)
- 128 or 96 kB Banked Flash; In-system programma-
ble in 512-byte Sectors
- External 64 kB data memory interface programma-
ble for multiplexed or non-multiplexed mode
Digital Peripherals
- 40, 33, or 25 Port I/O; All 5 V push-pull with high
sink current
- CAN 2.0 Controller—no crystal required
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Two Hardware enhanced UARTs, SMBus™, and
enhanced SPI™ serial ports
- Six general purpose 16-bit counter/timers
- Two 16-Bit programmable counter array (PCA)
peripherals with six capture/compare modules each
and enhanced PWM functionality
Clock Sources
- Internal 24 MHz with ±0.5% accuracy for CAN and
master LIN operation.
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
- 48-Pin QFP/QFN (C8051F580/1/4/5)
- 40-Pin QFN (C8051F588/9-F590/1)
- 32-Pin QFP/QFN (C8051F582/3/6/7)
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
X ADC
TEMP
SENSOR
Voltage VREG
Comparators 0-2 VREF
DIGITAL I/O
UART 0-1
SMBus
SPI
PCA x 2
Timers 0-5
CAN
LIN
Ports 0-4
Crossbar
External
Memory
Interface
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
128 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
8 kB XRAM
POR WDT
Rev. 1.2 4/11
Copyright © 2011 by Silicon Laboratories C8051F580/1/2/3/4/5/6/7/8/9-F590/1
Free Datasheet http://www.Datasheet4U.com







C8051F59x pdf, 数据表
C8051F58x/F59x
28.4. Watchdog Timer Mode .................................................................................. 322
28.4.1. Watchdog Timer Operation ................................................................... 322
28.4.2. Watchdog Timer Usage ........................................................................ 323
28.5. Register Descriptions for PCA0..................................................................... 325
29. Programmable Counter Array 1 (PCA1)............................................................. 331
29.1. PCA1 Counter/Timer ..................................................................................... 332
29.2. PCA1 Interrupt Sources................................................................................. 333
29.3. Capture/Compare Modules ........................................................................... 334
29.3.1. Edge-triggered Capture Mode............................................................... 335
29.3.2. Software Timer (Compare) Mode.......................................................... 336
29.3.3. High-Speed Output Mode ..................................................................... 337
29.3.4. Frequency Output Mode ....................................................................... 338
29.3.5. 8-bit, 9-bit, 10-bit and 11-bit Pulse Width Modulator Modes ................. 339
29.3.5.1. 8-bit Pulse Width Modulator Mode................................................ 339
29.3.5.2. 9/10/11-bit Pulse Width Modulator Mode...................................... 341
29.3.6. 16-Bit Pulse Width Modulator Mode...................................................... 342
29.4. Register Descriptions for PCA1..................................................................... 343
30. C2 Interface .......................................................................................................... 349
30.1. C2 Interface Registers................................................................................... 349
30.2. C2 Pin Sharing .............................................................................................. 353
Document Change List ............................................................................................. 354
Contact Information .................................................................................................. 356
8 Rev. 1.2
Free Datasheet http://www.Datasheet4U.com







C8051F59x equivalent, schematic
C8051F58x/F59x
SFR Definition 21.2. LIN0DAT: LIN0 Indirect Data Register ....................................... 219
SFR Definition 21.3. LIN0CF: LIN0 Control Mode Register ........................................ 220
SFR Definition 22.1. CAN0CFG: CAN Clock Configuration ........................................ 236
SFR Definition 23.1. SMB0CF: SMBus Clock/Configuration ...................................... 243
SFR Definition 23.2. SMB0CN: SMBus Control .......................................................... 245
SFR Definition 23.3. SMB0DAT: SMBus Data ............................................................ 247
SFR Definition 24.1. SCON0: Serial Port 0 Control .................................................... 259
SFR Definition 24.2. SMOD0: Serial Port 0 Control .................................................... 260
SFR Definition 24.3. SBUF0: Serial (UART0) Port Data Buffer .................................. 261
SFR Definition 24.4. SBCON0: UART0 Baud Rate Generator Control ...................... 261
SFR Definition 24.6. SBRLL0: UART0 Baud Rate Generator Reload Low Byte ........ 262
SFR Definition 24.5. SBRLH0: UART0 Baud Rate Generator Reload High Byte ....... 262
SFR Definition 25.1. SCON1: Serial Port 1 Control .................................................... 267
SFR Definition 25.2. SBUF1: Serial (UART1) Port Data Buffer .................................. 268
SFR Definition 26.1. SPI0CFG: SPI0 Configuration ................................................... 277
SFR Definition 26.2. SPI0CN: SPI0 Control ............................................................... 278
SFR Definition 26.3. SPI0CKR: SPI0 Clock Rate ....................................................... 279
SFR Definition 26.4. SPI0DAT: SPI0 Data ................................................................. 279
SFR Definition 27.1. CKCON: Clock Control .............................................................. 284
SFR Definition 27.2. TCON: Timer Control ................................................................. 289
SFR Definition 27.3. TMOD: Timer Mode ................................................................... 290
SFR Definition 27.4. TL0: Timer 0 Low Byte ............................................................... 291
SFR Definition 27.5. TL1: Timer 1 Low Byte ............................................................... 291
SFR Definition 27.6. TH0: Timer 0 High Byte ............................................................. 292
SFR Definition 27.7. TH1: Timer 1 High Byte ............................................................. 292
SFR Definition 27.8. TMR2CN: Timer 2 Control ......................................................... 296
SFR Definition 27.9. TMR2RLL: Timer 2 Reload Register Low Byte .......................... 297
SFR Definition 27.10. TMR2RLH: Timer 2 Reload Register High Byte ...................... 297
SFR Definition 27.11. TMR2L: Timer 2 Low Byte ....................................................... 298
SFR Definition 27.12. TMR2H Timer 2 High Byte ....................................................... 298
SFR Definition 27.13. TMR3CN: Timer 3 Control ....................................................... 302
SFR Definition 27.14. TMR3RLL: Timer 3 Reload Register Low Byte ........................ 303
SFR Definition 27.15. TMR3RLH: Timer 3 Reload Register High Byte ...................... 303
SFR Definition 27.16. TMR3L: Timer 3 Low Byte ....................................................... 304
SFR Definition 27.17. TMR3H Timer 3 High Byte ....................................................... 304
SFR Definition 27.18. TMRnCN: Timer 4 and 5 Control ............................................. 308
SFR Definition 27.19. TMRnCF: Timer 4 and 5 Configuration .................................... 309
SFR Definition 27.20. TMRnCAPL: Timer 4 and 5 Capture Register Low Byte ......... 310
SFR Definition 27.21. TMRnCAPH: Timer 4 and 5 Capture Register High Byte ........ 310
SFR Definition 27.22. TMRnL: Timer 4 and 5 Low Byte ............................................. 311
SFR Definition 27.23. TMRnH Timer 4 and 5 High Byte ............................................. 311
SFR Definition 28.1. PCA0CN: PCA0 Control ............................................................ 325
SFR Definition 28.2. PCA0MD: PCA0 Mode .............................................................. 326
SFR Definition 28.3. PCA0PWM: PCA0 PWM Configuration ..................................... 327
SFR Definition 28.4. PCA0CPMn: PCA0 Capture/Compare Mode ............................ 328
16 Rev. 1.2
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