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PDF ( 数据手册 , 数据表 ) ASC8848

零件编号 ASC8848
描述 (ASC8848 - ASC8851) Multimedia SoC
制造商 NXP Semiconductors
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ASC8848 数据手册, 描述, 功能
ASC8848; ASC8849; ASC8850;
ASC8851
Multimedia SoC
Rev. 2.06 — 24 September 2011
Data sheet
1. General description
NXPs ASC8848/49/50/51 SoC is a single chip platform that is designed for embedded
multimedia communication, security and entertainment applications. Powered by the most
popular ARM926EJ processor and high performance NXP video hardware accelerators,
ASC8848/49/50/51 SoC could provide upto 1080p @ 45fps MPEG-4 AVC (H.264) and
JPEG encoding simultaneously at 1080p @ 40fps. With its built-in high performance
image front-end processing engine, it can also provide better video quality than any smart
sensor. Due to its highly flexible architecture, multiple stream real time encoding with up to
8x D1 (704x480) resolution is also practicable.
Version 2.0 of ASC8848/49/50/51 datasheet highlights the feature differences of
ASC8848/49/50 with respect to ASC8851. It also provides details on ASC8851 pinouts.
Free Datasheet http://www.Datasheet4U.com







ASC8848 pdf, 数据表
NXP Semiconductors
ASC8848_49_50_51
Multimedia SoC
5. Pinning information
5.1 Pinning
All ASC8849/50/51 SoC signals are listed in Table 6 and ASC8848 SoC signals are listed
in Table 8. ASC8848/49/50 SoC has input pins (I), output pins (O), bi-directional pins (I/O),
power pins (P), and ground pins (G). Some functional pins have built-in functions as
specified at Table 6. Table 4 explains each I/O functions used in Table 6. The ball map is
split to four quadrants as shown in Figure 2 to Figure 5.
1 2 3 4 5 6 7 8 9 10 11
A
UARTC_0
_I_SDA
UARTC_0
_O_SDA
UARTC_0
_IO_nDTR
GMAC_I
_RXD[6]
GMAC_I GMAC_I_ GMAC_I_ GMAC_O GMAC_O
_RX_CLK RXD[2] TX_CLK _TXD[5] _TX_CLK
GMAC_O
_TXD[0]
VSSIO_
2_5_3_3
B
SYS_I_
OSC_1_
CLK
UARTC_0 UARTC_0 GMAC_I_ GMAC_I_ GMAC_I_ GMAC_I_ GMAC_O GMAC_O
_I_nDCD _I_nCTS RXD[7] RXD[5] RXD[3] RXD[0] _TXD[6] _TXD[3]
GMAC_O
_TXD[1]
SYS_O_
MON_
CLK[1]
C
SYS_O_
OSC_1_
FEBCLK
UARTC_0 UARTC_0 UARTC_0 GMAC_I_ GMAC_I_ GMAC_I_ GMAC_O GMAC_O
_I_nRI _I_nDSR _IO_nRTS CRS
RXD[4] RXD[1] _TXD[7] _TXD[4]
GMAC_O
_TXD[2]
SYS_O_
MON_
CLK[0]
D
UARTC_2
_O_SDA
UARTC_2
_I_SDA
UARTC_1 UARTC_1 GMAC_I_
_I_SDA _IO_nDTR COL
GMAC_IO
_MD
GMAC_O
_MDC
GMAC_I_
RXDV
GMAC_I_
RXER
GMAC_O
_TXER
GMAC_O
_TXEN
E
VSSIO_
2_5_3_3
UARTC_1 UARTC_1 UARTC_1
_I_nDSR _O_SDA _I_nDCD
VDDIO_
3_3
VDDIO_
2_5_3_3
VDDIO_
2_5_3_3
VDDIO_
2_5_3_3
VDDIO_
2_5_3_3
VDDIO_
2_5_3_3
VDDIO_
3_3
F
USBC_IO
_PHY_DM
UARTC_1
_I_nRI
UARTC_1
_I_nCTS
UARTC_1
_IO_nRTS
VDDIO_
3_3
VSSIO_
2_5_3_3
PLLC_I_
PLL_2_
PWR_
VSSA_2_5
VSSIO_
2_5_3_3
G
USBC_IO
_PHY_DP
USBC_IO
_PHY_
ATEST
USBC_O
_DRV_
VBUS
USBC_IO USBC_IO_ PLLC_I_
UARTC_3 _PHY_ PHY_PWR PLL_2_
_I_SDA PWR_ _VSSA_ PWR_
VDDA _3_3 2_5_3_3 VDDA_2_5
VDDIO_
3_3
H
VSSIO_
2_5_3_3
USBC_IO
_PHY_
VBUS
USBC_I_
PHY_ID
UARTC_3
_O_SDA
USBC_IO USBC_IO_
_PHY_ PHY_PWR
PWR_ _VSSA_
VDDC_1_0 2_5_3_3
VDDIO_
3_3
VDDC_
1_0
J
I2SSC_0_
I_BCLK
I2SSC_0_
I_WS
I2SSC_0_
O_TXD
USBC_IO_
PHY_REXT
RKELVIN
USBC_IO
_PHY_
PWR_
VDDA _2_5
USBC_IO_
PHY_PWR
_VSSC_
1_0
VSSIO_
2_5_3_3
VDDC_
1_0
K
I2SSC_1_
I_WS
I2SSC_1_
I_BCLK
I2SSC_0_
I_RXD
SYS_I_
BOOT_
MODE_
SEL[0]
reserved reserved
VDDIO_
3_3
VDDC_
1_0
L
I2SSC_O_
TX_MCLK
I2SSC_2_
I_WS
I2SSC_1_
I_RXD
SYS_I_
BOOT_
MODE_
SEL[1]
reserved reserved
VDDIO_
3_3
VDDC_
1_0
VSSIO_
2_5_3_3
VSSIO_
2_5_3_3
VDDC_
1_0
VSSC_
1_0
VSSC_
1_0
VSSC_
1_0
VSSIO_
2_5_3_3
VSSIO_
2_5_3_3
VDDC_
1_0
VSSC_
1_0
VSSC_
1_0
VSSC_
1_0
VDDIO_
3_3
VSSIO_
2_5_3_3
VDDC_
1_0
VSSC_
1_0
VSSC_
1_0
VSSC_
1_0
001aam935
Remark: Pin Assignment is for the M2 version. For the M1 version refer to Table 6
Fig 2. Top left view of an ASC8849 / 8850 / 8851 TFBGA-484 pin assignment
ASC8848_49_50_51
Data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.06 — 24 September 2011
© NXP B.V. 2011. All rights reserved.
8 of 263
Free Datasheet http://www.Datasheet4U.com







ASC8848 equivalent, schematic
NXP Semiconductors
ASC8848_49_50_51
Multimedia SoC
5.2 Pin description
Table 4. I/O functions
I/O function
Description
5VT 5 V - tolerant I/O
SMT
Schmitt trigger
I2P Default 2 mA driving capability and can be programmed to 2 mA, 4 mA, 8 mA and 12 mA
I4P Default 4 mA driving capability and can be programmed to 2 mA, 4 mA, 8 mA and 12 mA
I8P Default 8mA driving capability and can be programmed to 2 mA, 4 mA, 8 mA and 12 mA
PD Pulled down and can not be programmed.
PUDP
Pull-up disabled and can be programmed
PUEP
Pull-up enabled and can be programmed
PDDP
Pull-down disabled and can be programmed
PDEP
Pull-down enabled and can be programmed
OEDP
Output enable disabled and can be programmed
OEEP
Output enable enabled and can be programmed
IEEP
Input enable enabled and can be programmed
FSRP
Fast slew rate and can be programmed to slow
Table 5.
Ball
P4
R4
M5
W6
W17
W3
R7
T7
H6
J6
B11
V11
U6
N17
H17
Overview of ball map updates for ASC8848/49/50/51 M2 version and ASC8851
ASC8848/49/50 M1 version
ASC8848/49/50 M2 version and ASC8851
SYS_I_GMAC_MODE_SEL
VSSC_1_0
Reserved
DDR32SDMC_IO_PWR_VSSIO_1_8
SYS_I_GMAC_TX_CLK_DIR
VSSIO_2_5_3_3
DDR2SDMC_I_CMD_CALI
DDR32SDMC_O_PHY_ATEST
DDR2SDMC_I_DATA_1_CALI
DDR32SDMC_IO_PHY_PWR_VDDA_2_5
DDR2SDMC_I_DATA_0_CALI
DDR32SDMC_I_CALI
DDR2SDMC_IO_PHY_PWR_VDDC_1_0
VDDC_1_0
DDR2SDMC_IO_PHY_PWR_VSSC_1_0
DDR32SDMC_IO_PHY_PWR_VSSA_2_5
USBC_IO_PHY_PWR_VSSC_1_0
USBC_IO_PHY_PWR_VSSA_2_5_3_3
USBC_IO_PHY_PWR_VSSA_2_5_3_3
USBC_IO_PHY_PWR_VSSC_1_0
SYS_O_MON_CLK[1][1]
SYS_O_MON_CLK[1][1]
DDR2DMC_O_PHY_ATEST
DDR32DMC_O_ADDR[15]
DDR2SDMC_IO_PWR_VSSIO_1_8
DDR32DMC_O_nRST
VSSIO_2_5_3_3
VOC_I_CLK
VDDIO_3_3
VDDIO_SENSOR
[1] Refer to Table 7 for change
ASC8848_49_50_51
Data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.06 — 24 September 2011
© NXP B.V. 2011. All rights reserved.
16 of 263
Free Datasheet http://www.Datasheet4U.com










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