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PDF ( 数据手册 , 数据表 ) RMLV0408EGSP-5S2

零件编号 RMLV0408EGSP-5S2
描述 4Mb Advanced LPSRAM (512k word x 8bit)
制造商 Renesas
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RMLV0408EGSP-5S2 数据手册, 描述, 功能
RMLV0408E Series
4Mb Advanced LPSRAM (512k word × 8bit)
Preliminary
R10DS0217EJ0001
Rev.0.01
2013.09.10
Description
The RMLV0408E Series is a family of 4-Mbit static RAMs organized 524,288-word × 8-bit, fabricated by Renesas’s
high-performance Advanced LPSRAM technologies. The RMLV0408E Series has realized higher density, higher
performance and low power consumption. The RMLV0408E Series offers low power standby power dissipation;
therefore, it is suitable for battery backup systems. It is offered in 32-pin SOP, 32-pin TSOP II or 32-pin STSOP.
Features
Single 3V supply: 2.7V to 3.6V
Access time: 45/55ns (max.)
Current consumption:
── Standby: 0.4µA (typ.)
Equal access and cycle times
Common data input and output
── Three state output
Directly TTL compatible
── All inputs and outputs
Battery backup operation
Part Name Information
Part Name
RMLV0408EGSP-4S2
Access
time
45 ns
RMLV0408EGSP-5S2
55 ns
RMLV0408EGSB-4S2
45 ns
RMLV0408EGSB-5S2
55 ns
RMLV0408EGSA-4S2
RMLV0408EGSA-5S2
45 ns
55 ns
Temperature
Range
-40 ~ +85°C
Package
525-mil 32-pin plastic SOP
400-mil 32-pin plastic TSOP II
8mm x 13.4mm STSOP
R10DS0217EJ0001 Rev.0.01
2013.09.10
Page 1 of 10
Free Datasheet http://www.Datasheet4U.com







RMLV0408EGSP-5S2 pdf, 数据表
RMLV0408E Series
Write Cycle (2) (WE# CLOCK, OE# Low Fixed)
A0~18
tWC
Valid address
CS#
WE#
OE#
OE# = “L” level VIL
I/O0~7
tAW
tAS
tCW
tWP *18,
tWR
tWHZ *19,20
tOW
*21 Valid Data
tDW tDH
Preliminary
*21
Note
18. tWP is the interval between write start and write end.
A write starts when both of CS# and WE# become active.
A write is performed during the overlap of a low CS# and a low WE#.
A write ends when any of CS# or WE# becomes inactive.
19. tWHZ is defined as the time when the I/O pins enter a high-impedance state and are not referred to the I/O
levels.
20. This parameter is sampled and not 100% tested.
21. During this period, I/O pins are in the output state so input signals must not be applied to the I/O pins.
R10DS0217EJ0001 Rev.0.01
2013.09.10
Page 8 of 10
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