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PDF ( 数据手册 , 数据表 ) ST72321Rx

零件编号 ST72321Rx
描述 64/44-pin 8-bit MCU
制造商 STMicroelectronics
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ST72321Rx 数据手册, 描述, 功能
ST72321Rx
ST72321ARx ST72321Jx
64/44-pin 8-bit MCU with 32 to 60K Flash/ROM, ADC,
five timers, SPI, SCI, I2C interface
Features
Memories
– 32K to 60K dual voltage High Density Flash
(HDFlash) or ROM with read-out protection
capability. In-Application Programming and
In-Circuit Programming for HDFlash devices
– 1K to 2K RAM
– HDFlash endurance: 100 cycles, data reten-
tion: 40 years at 85°C
Clock, Reset And Supply Management
– Enhanced low voltage supervisor (LVD) for
main supply and auxiliar voltage detector
(AVD) with interrupt capability
– Clock sources: crystal/ceramic resonator os-
cillators, internal RC oscillator and bypass for
external clock
– PLL for 2x frequency multiplication
– Four Power Saving Modes: Halt, Active-Halt,
Wait and Slow
Interrupt Management
– Nested interrupt controller
– 14 interrupt vectors plus TRAP and RESET
– Top Level Interrupt (TLI) pin on 64-pin devices
– 15/9 external interrupt lines (on 4 vectors)
Up to 48 I/O Ports
– 48/32/24 multifunctional bidirectional I/O lines
– 34/22/17 alternate function lines
– 16/12/10 high sink outputs
5 Timers
– Main Clock Controller with: Real time base,
Beep and Clock-out capabilities
– Configurable watchdog timer
– Two 16-bit timers with: 2 input captures, 2 out-
put compares, external clock input on one tim-
er, PWM and pulse generator modes
LQFP64
14 x 14
LQFP32
7x7
LQFP64
10 x 10
LQFP44
10 x 10
– 8-bit PWM Auto-reload timer with: 2 input cap-
tures, 4 PWM outputs, output compare and
time base interrupt, external clock with event
detector
3 Communications Interfaces
– SPI synchronous serial interface
– SCI asynchronous serial interface
– I2C multimaster interface
1 Analog peripheral
– 10-bit ADC with up to 16 input ports
Instruction Set
– 8-bit Data Manipulation
– 63 Basic Instructions
– 17 main Addressing Modes
– 8 x 8 Unsigned Multiply Instruction
Development Tools
– Full hardware/software development package
– In-Circuit Testing capability
Table 1. Device summary
Features
Program memory - bytes
RAM (stack) - bytes
Operating Voltage
Temp. Range
Package
ST72321R9/ST72321AR9/ ST72321R7/ST72321AR7/
ST72321J9
ST72321J7
ST72321R6/ST72321AR6
Flash/ROM 60K
Flash/ROM 48K
Flash/ROM 32K
2048 (256)
1536 (256)
1024 (256)
3.8 to 5.5V
-40 to +125°C, -40 to +85°C
LQFP64 14x14 (R), LQFP64 10x10 (AR), LQFP44 10x10 (J)
March 2009
Rev 2
1/193
1
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ST72321Rx pdf, 数据表
ST72321Rx ST72321ARx ST72321Jx
2 PIN DESCRIPTION
Figure 2. 64-Pin LQFP 14x14 and 10x10 Package Pinout
(HS) PE4
(HS) PE5
(HS) PE6
(HS) PE7
PWM3 / PB0
PWM2 / PB1
PWM1 / PB2
PWM0 / PB3
ARTCLK / (HS) PB4
ARTIC1 / PB5
ARTIC2 / PB6
PB7
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4
45
ei0
5 44
6
7 ei2
43
42
8 41
9 40
10
11 ei3
39
38
12 37
13 36
14 35
15 ei1 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1
VDD_1
PA3 (HS)
PA2
PA1
PA0
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
VSS_0
VDD_0
(HS) 20mA high sink capability
eix associated external interrupt vector
8/193
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ST72321Rx equivalent, schematic
ST72321Rx ST72321ARx ST72321Jx
Address
Block
Register
Label
Register Name
Reset
Status
Remarks
002Ah
002Bh
002Ch
002Dh
002Eh
to
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
WATCHDOG WDGCR
SICSR
MCC
MCCSR
MCCBCR
Watchdog Control Register
7Fh R/W
System Integrity Control/Status Register
000x 000x b R/W
Main Clock Control / Status Register
00h R/W
Main Clock Controller: Beep Control Register 00h
R/W
Reserved Area (3 Bytes)
TIMER A
TIMER B
SCI
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
00h
00h
xxxx x0xx b
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
Reserved Area (1 Byte)
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
00h
00h
xxxx x0xx b
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR
SCIETPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register
C0h
xxh
00h
x000 0000b
00h
00h
---
00h
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
16/193
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