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零件编号 | 74HC595 | ||
描述 | 8-bit serial-in serial or parallel-out shift register | ||
制造商 | NXP Semiconductors | ||
LOGO | |||
1 Page
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 8 — 25 February 2016
Product data sheet
1. General description
The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a
storage register and 3-state outputs. Both the shift and storage register have separate
clocks. The device features a serial input (DS) and a serial output (Q7S) to enable
cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register.
Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift
register is transferred to the storage register on a LOW-to-HIGH transition of the STCP
input. If both clocks are connected together, the shift register will always be one clock
pulse ahead of the storage register. Data in the storage register appears at the output
whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to
assume a high-impedance OFF-state. Operation of the OE input does not affect the state
of the registers. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
Complies with JEDEC standard no. 7A
Input levels:
For 74HC595: CMOS level
For 74HCT595: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
40 C to +85 C
Min Typ Max
74HCT595
VIH
HIGH-level
VCC = 4.5 V to 5.5 V
input voltage
2.0 1.6
-
VIL
LOW-level
VCC = 4.5 V to 5.5 V
input voltage
- 1.2 0.8
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage all outputs
IO = 20 A
Q7S output
4.4 4.5
-
IO = 4 mA
Qn bus driver outputs
3.84 4.32
-
IO = 6 mA
VOL LOW-level VI = VIH or VIL; VCC = 4.5 V
output voltage all outputs
3.7 4.32
-
IO = 20 A
Q7S output
- 0 0.1
IO = 4.0 mA
Qn bus driver outputs
- 0.15 0.33
IO = 6.0 mA
- 0.16 0.33
II input leakage VI = VCC or GND; VCC = 5.5 V - - 1.0
current
IOZ
ICC
ICC
OFF-state
output current
supply current
additional
supply current
VI = VIH or VIL; VCC = 5.5 V;
VO = VCC or GND
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
per input pin; IO = 0 A; VI = VCC
2.1 V; other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
pins MR, SHCP, STCP, OE
-
-
-
- 5.0
- 80
150 675
pin DS
- 25 113
CI input
capacitance
- 3.5 -
40 C to +125 C Unit
Min Max
2.0 - V
- 0.8 V
4.4 - V
3.7 - V
3.7 - V
- 0.1 V
- 0.4 V
- 0.4 V
- 1.0 A
- 10 A
- 160 A
- 735 A
- 123 A
- - pF
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 23
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
13. Package outline
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74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
16 of 23
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页数 | 23 页 | ||
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