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PDF ( 数据手册 , 数据表 ) STM32F303VC

零件编号 STM32F303VC
描述 ARM Cortex-M4F 32b MCU+FPU
制造商 STMicroelectronics
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STM32F303VC 数据手册, 描述, 功能
STM32F303xB STM32F303xC
ARM®-based Cortex®-M4 32b MCU+FPU, up to 256KB Flash+
48KB SRAM, 4 ADCs, 2 DAC ch., 7 comp, 4 PGA, timers, 2.0-3.6 V
Datasheet - production data
Features
Core: ARM® Cortex®-M4 32-bit CPU with FPU
(72 MHz max), single-cycle multiplication and
HW division, 90 DMIPS (from CCM), DSP
instruction and MPU (memory protection unit)
Operating conditions:
– VDD, VDDA voltage range: 2.0 V to 3.6 V
Memories
– 128 to 256 Kbytes of Flash memory
– Up to 40 Kbytes of SRAM, with HW parity
check implemented on the first 16 Kbytes.
– Routine booster: 8 Kbytes of SRAM on
instruction and data bus, with HW parity
check (CCM)
CRC calculation unit
Reset and supply management
– Power-on/Power-down reset (POR/PDR)
– Programmable voltage detector (PVD)
– Low-power modes: Sleep, Stop and Standby
– VBAT supply for RTC and backup registers
Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x 16 PLL option
Internal 40 kHz oscillator
Up to 87 fast I/Os
– All mappable on external interrupt vectors
– Several 5 V-tolerant
Interconnect matrix
12-channel DMA controller
Four ADCs 0.20 µS (up to 39 channels) with
selectable resolution of 12/10/8/6 bits, 0 to
3.6 V conversion range, single
ended/differential input, separate analog supply
from 2 to 3.6 V
Two 12-bit DAC channels with analog supply
from 2.4 to 3.6 V
Seven fast rail-to-rail analog comparators with
analog supply from 2 to 3.6 V
Four operational amplifiers that can be used in
PGA mode, all terminals accessible with analog
supply from 2.4 to 3.6 V
Up to 24 capacitive sensing channels supporting
touchkey, linear and rotary touch sensors
LQFP48 (7 × 7 mm)
LQFP64 (10 × 10 mm)
WLCSP100 (0.4 mm pitch)
LQFP100 (14 × 14 mm)
Up to 13 timers
– One 32-bit timer and two 16-bit timers with
up to 4 IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– Two 16-bit 6-channel advanced-control
timers, with up to 6 PWM channels,
deadtime generation and emergency stop
– One 16-bit timer with 2 IC/OCs, 1
OCN/PWM, deadtime generation and
emergency stop
– Two 16-bit timers with IC/OC/OCN/PWM,
deadtime generation and emergency stop
– Two watchdog timers (independent, window)
– SysTick timer: 24-bit downcounter
– Two 16-bit basic timers to drive the DAC
Calendar RTC with Alarm, periodic wakeup
from Stop/Standby
Communication interfaces
– CAN interface (2.0B Active)
– Two I2C Fast mode plus (1 Mbit/s) with
20 mA current sink, SMBus/PMBus, wakeup
from STOP
– Up to five USART/UARTs (ISO 7816
interface, LIN, IrDA, modem control)
– Up to three SPIs, two with multiplexed
half/full duplex I2S interface, 4 to 16
programmable bit frames
– USB 2.0 full speed interface
Infrared transmitter
Serial wire debug, Cortex®-M4 with FPU ETM,
JTAG
96-bit unique ID
Table 1. Device summary
Reference
Part number
STM32F303xB
STM32F303xC
STM32F303CB, STM32F303RB, STM32F303VB
STM32F303CC, STM32F303RC, STM32F303VC
May 2016
This is information on a product in full production.
DocID023353 Rev 13
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STM32F303VC pdf, 数据表
List of figures
STM32F303xB STM32F303xC
Figure 49.
Figure 50.
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
WLCSP100, 0.4 mm pitch wafer level chip scale package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
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STM32F303VC equivalent, schematic
Functional overview
STM32F303xB STM32F303xC
3.7.4
Note:
Low-power modes
The STM32F303xB/STM32F303xC supports three low-power modes to achieve the best
compromise between low-power consumption, short startup time and available wakeup
sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low-power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC
alarm, COMPx, I2Cx or U(S)ARTx.
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin or an RTC alarm occurs.
The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
3.8
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Table 4. STM32F303xB/STM32F303xC peripheral interconnect matrix
Interconnect source
Interconnect
destination
Interconnect action
TIMx
Timers synchronization or chaining
TIMx
ADCx
DAC1
DMA
Conversion triggers
Memory to memory transfer trigger
Compx
Comparator output blanking
COMPx
TIMx
Timer input: OCREF_CLR input, input capture
ADCx
TIMx
Timer triggered by analog watchdog
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