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PDF ( 数据手册 , 数据表 ) AX250

零件编号 AX250
描述 Axcelerator Family FPGAs
制造商 Actel
LOGO Actel LOGO 


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AX250 数据手册, 描述, 功能
Axcelerator Family FPGAs
v2.7
ue
Leading-Edge Performance
• 350+ MHz System Performance
• 500+ MHz Internal Performance
• High-Performance Embedded FIFOs
• 700 Mb/s LVDS Capable I/Os
Specifications
• Up to 2 Million Equivalent System Gates
• Up to 684 I/Os
• Up to 10,752 Dedicated Flip-Flops
• Up to 295 kbits Embedded SRAM/FIFO
• Manufactured on Advanced 0.15 μm CMOS Antifuse
Process Technology, 7 Layers of Metal
Features
• Single-Chip, Nonvolatile Solution
• Up to 100% Resource Utilization with 100% Pin Locking
• 1.5V Core Voltage for Low Power
• Footprint Compatible Packaging
• Flexible, Multi-Standard I/Os:
– 1.5V, 1.8V, 2.5V, 3.3V Mixed Voltage Operation
– Bank-Selectable I/Os – 8 Banks per Chip
– Single-Ended I/O Standards: LVTTL, LVCMOS, 3.3V
PCI, and 3.3V PCI-X
– Differential I/O Standards: LVPECL and LVDS
Table 1-1 • Axcelerator Family Product Profile
Device
Capacity (in Equivalent System Gates)
Typical Gates
Modules
Register (R-cells)
Combinatorial (C-cells)
Maximum Flip-Flops
Embedded RAM/FIFO
Number of Core RAM Blocks
Total Bits of Core RAM
Clocks (Segmentable)
Hardwired
Routed
PLLs
I/Os
I/O Banks
Maximum User I/Os
Maximum LVDS Channels
Total I/O Registers
Package
CSP
PQFP
BGA
FBGA
CQFP
CCGA
AX125
125,000
82,000
672
1,344
1,344
4
18,432
4
4
8
8
168
84
504
180
256, 324
– Voltage-Referenced I/O Standards: GTL+, HSTL
Class 1, SSTL2 Class 1 and 2, SSTL3 Class 1 and 2
– Registered I/Os
– Hot-Swap Compliant I/Os (except PCI)
– Programmable Slew Rate and Drive Strength on
Outputs
– Programmable Delay and Weak Pull-Up/Pull-Down
Circuits on Inputs
• Embedded Memory:
– Variable-Aspect 4,608-bit RAM Blocks (x1, x2, x4,
x9, x18, x36 Organizations Available)
– Independent, Width-Configurable Read and Write Ports
– Programmable Embedded FIFO Control Logic
• Segmentable Clock Resources
• Embedded Phase-Locked Loop:
– 14-200 MHz Input Range
– Frequency Synthesis Capabilities up to 1 GHz
• Deterministic, User-Controllable Timing
• Unique In-System Diagnostic and Debug Capability
with Actel Silicon Explorer II
• Boundary-Scan Testing Compliant with IEEE Standard
1149.1 (JTAG)
• FuseLockTM Secure Programming Technology
Prevents Reverse Engineering and Design Theft
AX250
250,000
154,000
1,408
2,816
2,816
12
55,296
4
4
8
8
248
124
744
208
256, 484
208, 352
AX500
500,000
286,000
2,688
5,376
5,376
16
73,728
4
4
8
8
336
168
1,008
AX1000
1,000,000
612,000
6,048
12,096
12,096
36
165,888
4
4
8
8
516
258
1,548
AX2000
2,000,000
1,060,000
10,752
21,504
21,504
64
294,912
4
4
8
8
684
342
2,052
208
484, 676
208, 352
729
484, 676, 896
352
624
896, 1152
352
624
November 2008
© 2008 Actel Corporation
i
*See Actel’s website for the latest version of the datasheet.
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AX250 pdf, 数据表
Axcelerator Family FPGAs
Figure 1-2 • Axcelerator Family Interconnect Elements
Logic Modules
Actel's Axcelerator family provides two types of logic
modules: the register cell (R-cell) and the combinatorial
cell (C-cell). The
can implement more than 4,000 combinatorial functions
of up to five inputs (Figure 1-3 on page 1-3).
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and active-low enable control
signals (Figure 1-3 on page 1-3). The R-cell registers
feature programmable clock polarity selectable on a
register-by-register basis. This provides additional
flexibility (e.g., easy mapping of dual-data-rate functions
into the FPGA) while conserving valuable clock resources.
The clock source for the R-cell can be chosen from the
hardwired clocks, routed clocks, or internal logic.
Two C-cells, a single R-cell, and two Transmit (TX) and two
Receive (RX) routing buffers form a Cluster, while two
Clusters comprise a SuperCluster (Figure 1-4 on page 1-3).
Each SuperCluster also contains an independent Buffer (B)
module, which supports buffer insertion on high-fanout
nets by the place-and-route tool, minimizing system
delays while improving logic utilization.
The logic modules within the SuperCluster are arranged
so that two combinatorial modules are side-by-side,
giving a C–C–R – C–C–R pattern to the SuperCluster. This
C–C–R pattern enables efficient implementation
(minimum delay) of two-bit carry logic for improved
arithmetic performance (Figure 1-5 on page 1-3).
The AX architecture is fully fracturable, meaning that if
one or more of the logic modules in a SuperCluster are
used by a particular signal path, the other logic modules
are still available for use by other paths.
At the chip level, SuperClusters are organized into core
tiles, which are arrayed to build up the full chip. For
example, the AX1000 is composed of a 3x3 array of nine
core tiles. Surrounding the array of core tiles are blocks
of I/O Clusters and the I/O bank ring (Table 1-1 on
page 1-3). Each core tile consists of an array of 336
SuperClusters and four SRAM blocks (176 SuperClusters
and three SRAM blocks for the AX250). The SRAM blocks
are arranged in a column on the west side of the tile
(Figure 1-6 on page 1-4).
1-2 v2.7
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AX250 equivalent, schematic
Axcelerator Family FPGAs
Calculating Power Dissipation
Table 2-3 • Standby Current
Device
AX125
Temperature
Typical at 25°C
ICCA
Standby
Current
(Core)
1.5
ICCDA
Standby
Current,
Differential
I/O
1.5
ICCBANK
Standby Current per
I/O Bank
2.5V VCCI 3.3V VCCI
0.2 0.3
ICCPLL
Standby
Current
per PLL
0.2
ICCCP
Standby Current,
Charge Pump
Bypassed
Active
Mode
0.3 0.01
Units
mA
70°C
15
6
0.5 0.75
1
0.4 0.01 mA
85°C 25 6 0.6 0.8 1 0.4 0.2 mA
125°C 50 8
1 1.5 2 0.4 0.5 mA
AX250 Typical at 25°C
1.5
1.4
0.25 0.4
0.2
0.3 0.01 mA
70°C 30 7 0.8 0.9 1 0.4 0.01 mA
85°C 40 7 0.8 1 1 0.4 0.2 mA
125°C
70
9
1.3 1.8 2 0.4 0.5 mA
AX500 Typical at 25°C
5
1.4
0.4 0.75 0.2
0.3 0.01 mA
70°C 60 7
1 1.5 1 0.4 0.01 mA
85°C 80 7
1 1.9 1 0.4 0.2 mA
125°C
180
9
1.75 2.5 1.5 0.4 0.5 mA
AX1000 Typical at 25°C
7.5
1.5
0.5 1.25 0.2
0.3 0.01 mA
70°C 80 8 1.5 3 1 0.4 0.01 mA
85°C 120 8
1.5 3.4 1 0.4 0.2 mA
125°C 200 10
3 4 1.5 0.4 0.5 mA
AX2000 Typical at 25°C
20
1.6
0.7 1.5 0.2 0.3 0.01 mA
70°C
160 10
2 7 1 0.4 0.01 mA
85°C
200 10
3 8 1 0.4 0.2 mA
125°C 500 15
4 10 1.5 0.4 0.5 mA
Note: ICCCP Active is the ICCDA or the Internal Charge Pump current. ICCCP Bypassed mode is the External Charge Pump current IIH (VPUMP
pin).
Table 2-4 • Default CLOAD/VCCI
Single-Ended without VREF
LVTTL 24mA High Slew
LVTTL 16mA High Slew
LVTTL 12mA High Slew
LVTTL 8mA High Slew
LVTTL 24mA Low Slew
LVTTL 16mA Low Slew
LVTTL 12mA Low Slew
LVTTL 8mA Low Slew
LVCMOS – 25
LVCMOS – 18
Note: *PI/O = P10 + CLOAD *VCCI2
CLOAD (pF)
35
35
35
35
35
35
35
35
35
35
VCCI (V)
PLOAD (μw/MHz) P10 (μw/MHz) PI/O (μW/MHz)*
3.3 381.2
3.3 381.2
3.3 381.2
3.3 381.2
3.3 381.2
3.3 381.2
3.3 381.2
3.3 381.2
2.5 218.8
1.8 113.4
262.6
220.1
160.9
125.4
164.2
145.9
133.6
113.8
143.2
68.7
643.7
601.3
542.1
506.5
545.4
527.0
514.8
494.9
361.9
182.1
2-2 v2.7
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