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PDF ( 数据手册 , 数据表 ) MAX191

零件编号 MAX191
描述 12-Bit Sampling ADC
制造商 Maxim Integrated
LOGO Maxim Integrated LOGO 


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MAX191 数据手册, 描述, 功能
19-4506; Rev 4; 2/97
EVFAOLLULAOTWIOSNDKAITTAMSAHNEUEATL
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
General Description
The MAX191 is a monolithic, CMOS, 12-bit analog-to-
digital converter (ADC) featuring differential inputs,
track/hold (T/H), internal voltage reference, internal or
external clock, and parallel or serial µP interface. The
MAX191 has a 7.5µs conversion time, a 2µs acquisition
time, and a guaranteed 100ksps sample rate.
The MAX191 operates from a single +5V supply or from
dual ±5V supplies, allowing ground-referenced bipolar
input signals. The device features a logic power-down
input, which reduces the 3mA VDD supply current to
50µA max, including the internal-reference current.
Decoupling capacitors are the only external compo-
nents needed for the power supply and reference. This
ADC operates with either an external reference, or an
internal reference that features an adjustment input for
trimming system gain errors.
The MAX191 provides three interface modes: two 8-bit
parallel modes, and a serial interface mode that is com-
patible with SPITM, QSPITM, and MICROWIRETM serial-
interface standards.
________________________Applications
Battery-Powered Data Logging
PC Pen Digitizers
High-Accuracy Process Control
Electromechanical Systems
Data-Acquisition Boards for PCs
Automatic Testing Systems
Telecommunications
Digital Signal Processing (DSP)
Functional Diagram
VREF 5
REFADJ 6
VDD
24
2.46V
REF
AIN + 3
AIN - 4
MAX191
7 12
AGND DGND
CLK/SCLK
23
OSC 3-STATE
OUTPUT
8-BIT
BUS
AND
12 SERIAL
I/O
IN REF OUT
12-BIT
SAR ADC
2
VSS
CONTROL
LOGIC
1 22 8
PD PAR BIP
18 D7/DOUT
17
16 D6/SCLKOUT
D5/SSTRB
15
D4
14 D3/D11
13 D2/D10
11
D1/D9
10 D0/D8
20 CS
19
9
21
RD
BUSY
HBEN
____________________________Features
o 12-Bit Resolution, 1/2LSB Linearity
o +5V or ±5V Operation
o Built-In Track/Hold
o Internal Reference with Adjustment Capability
o Low Power: 3mA Operating Mode
20µA Power-Down Mode
o 100ksps Tested Sampling Rate
o Serial and 8-Bit Parallel µP Interface
o 24-Pin Narrow DIP and Wide SO Packages
Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
ERROR
(LSB)
MAX191ACNG 0°C to +70°C 24 Narrow Plastic DIP ±1/2
MAX191BCNG 0°C to +70°C 24 Narrow Plastic DIP ±1
MAX191ACWG 0°C to +70°C 24 Wide SO
±1/2
MAX191BCWG 0°C to +70°C 24 Wide SO
±1
MAX191BC/D
0°C to +70°C Dice*
±1
MAX191AENG -40°C to +85°C 24 Narrow Plastic DIP ±1/2
MAX191BENG -40°C to +85°C 24 Narrow Plastic DIP ±1
MAX191AEWG -40°C to +85°C 24 Wide SO
±1/2
MAX191BEWG -40°C to +85°C 24 Wide SO
±1
MAX191AMRG -55°C to +125°C 24 Narrow CERDIP** ±1/2
MAX191BMRG -55°C to +125°C 24 Narrow CERDIP** ±1
* Dice are specified at TA = +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
Pin Configuration
TOP VIEW
PD 1
VSS 2
AIN+ 3
AIN- 4
VREF 5
REFADJ 6
AGND 7
BIP 8
BUSY 9
D0/D8 10
D1/D9 11
DGND 12
MAX191
24 VDD
23 CLK/SCLK
22 PAR
21 HBEN
20 CS
19 RD
18 D7/DOUT
17 D6/SCLKOUT
16 D5/SSTRB
15 D4
14 D3/D11
13 D2/D10
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
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MAX191 pdf, 数据表
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
+5V
3k
DN DN
3k CL
CL
DGND
DGND
a. High-Z to VOH and VOL to VOH
b. High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Access Time
+5V
3k
DN DN
3k 10pF
10pF
DGND
DGND
a. VOH to High-Z
b. VOL to High-Z
Figure 2. Load Circuits for Bus-Relinquish Time
4.7µF
OPEN 1 PD
VDD 24 +5V
CLK/SCLK 23 C1
3 AIN+
4
AIN-
PAR 22
HBEN 21
SERIAL/PARALLEL
INTERFACE MODE
0.1µF
5
VREF MAX191
6
REFADJ
CS 20
RD 19
µP CONTROL
INPUTS
7 AGND
0.1µF 8 BIP
D7/DOUT 18
D6/SCLKOUT 17
OUTPUT 9 BUSY
STATUS
10 DO/DB
D5/SSTRB 16
D4 15
11 D1/D9
D3/D11 14
12
DGND
VSS
D2/D10 13
2
0V TO -5V
µP DATA BUS
NOTE: C1 120pF GENERATES 1MHz NOMINAL CLOCK.
Figure 3. Operational Diagram
_______________Detailed Description
The MAX191 uses successive approximation and input
track/hold (T/H) circuitry to convert an analog input sig-
nal to a 12-bit digital output. Flexible control logic pro-
vides easy interface to microprocessors (µPs), so most
applications require only the addition of passive com-
ponents. No external hold capacitor is required for the
T/H. Figure 3 shows the MAX191 in its simplest opera-
tional configuration.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in the Equivalent Input Circuit
(Figure 4). A capacitor switching between the AIN+
and AIN- inputs acquires the signal at the ADC’s ana-
log input. At the end of the conversion, the capacitor
reconnects to AIN+ and charges to the input signal.
An external input buffer is usually not needed for low-
bandwidth input signals (<100Hz) because the ADC
disconnects from the input during the conversion. In
unbuffered applications, an input filter capacitor
reduces conversion noise, but also may limit input
bandwidth.
When converting a single-ended input signal, AIN-
should be connected to AGND. If a differential signal is
connected, consider that the configuration is pseudo
differential—only the signal side to the input channel is
held by the T/H. The return side (AIN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. Accomplish this
by connecting a 0.1µF capacitor from AIN- to AGND.
Analog Input—Track/Hold
The T/H enters its tracking mode when the ADC is des-
elected (CS pin is held high and BUSY pin is high).
Hold mode starts approximately 25ns after a conver-
sion is initiated. The variation in this delay from one
conversion to the next (aperture jitter) is about 50ps.
Figures 6–10 detail the T/H and interface timing for the
8 _______________________________________________________________________________________
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MAX191 equivalent, schematic
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
fSCLK(MAX) = (1/2) x 1/ (tsu(M) + t22)
where tsu(M) is the minimum data-setup time re-
quired at the serial data input to the µP. For example,
Motorola’s MC68HC11A8 data book specifies a 100ns
minimum data-setup time. Using the worst case for a
military grade part of t22 = 280ns (see Timing
Characteristics) and substituting in the above equation
indicates a maximum SCLK frequency of 1.3MHz.
Using the MAX191 with SPI, QSPI and
MICROWIRE Serial Interfaces
Figure 13 shows interface connections to the MAX191
for common serial-interface standards.
SPI and MICROWIRE (CPOL=0, CPHA=0)
The MAX191 is compatible with SPI, QSPI and
MICROWIRE serial-interface standards. When using SPI
or QSPI, two modes are available to interface with the
MAX191. You can set CPOL = 0 and CPHA = 0 (Figure
14a), or set CPOL = 1 and CPHA = 1 (Figure 14b). When
using CPOL = 0 and CPHA = 0, the conversion begins
on the first falling edge of SCLK following CS going low.
Data is available from DOUT on the rising edge of SCLK,
and transitions on the falling edge. Two consecutive
1-byte reads are required to get the full 12 bits from the
ADC. The first byte contains the following, in this order: a
leading unknown bit (DOUT will still be high-impedance
on the first bit), a 0, and the six MSBs. The second byte
contains the remaining six LSBs and two trailing 0s.
SPI (CPOL=1, CPHA=1)
Setting CPOL = 1 and CPHA = 1 starts the clock high
during a read instruction. The MAX191 will shift out a
leading 0 followed by the 12 data bits and three trailing
0s (Figure 14b).
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 12 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles required to clock in the
data (Figure 15).
TMS320 Serial Interface
Figure 13d shows the pin connections to interface the
MAX191 to the TMS320. Since the MAX191 makes data
available on the rising edge of SCLK and the TMS320
shifts data in on the falling edge of CLKR, use CLKX of the
DSP to drive SCLK, and CLKX to drive the DSP’s CLKR
input. The inverter’s propagation delay also provides more
data-setup time at the DSP. For example, with no inverter
delay, and using t22 = 280ns and fSCLK = 1.6MHz, the
available setup time before the SCLK transition is:
setup time = 1/ (2 x fSCLK) - t22 = 1/ (2 x 1.6E6) - 280ns = 32ns
This still exceeds the 13ns minimum DR setup time before
the CLKR goes low (tsu(DR)), however, a generic 74HC04
provides an additional 20ns setup time (see Figure 13d).
Figure 16 shows the DSP interface timing characteris-
tics. The DSP begins clocking data in on the falling
edge of CLKR after the falling edge of SSTRB.
SCLK
CS
1ST BYTE READ
2ND BYTE READ
DOUT HIGH-Z
LEADING MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
ZERO
a. CPOL = 0, CPHA = 0
SCLK
CS
HIGH-Z
DOUT HIGH-Z
LEADING MSB D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB
ZERO
b. CPOL = 1, CPHA = 1
Figure 14. SPI/MICROWIRE Serial-Interface Timing
16 ______________________________________________________________________________________
HIGH-Z
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