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PDF ( 数据手册 , 数据表 ) MX29GL256F

零件编号 MX29GL256F
描述 SINGLE VOLTAGE 3V ONLY FLASH MEMORY
制造商 MACRONIX
LOGO MACRONIX LOGO 


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MX29GL256F 数据手册, 描述, 功能
MX29GL256F
MX29GL256F
DATASHEET
P/N:PM1544
REV. 1.5, OCT. 30, 2013
1
http://www.Datasheet4U.com







MX29GL256F pdf, 数据表
BLOCK DIAGRAM
MX29GL256F
CE#
OE#
WE#
RESET#
BYTE#
WP#/ACC
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
A0-AM
ADDRESS
LATCH
AND
BUFFER
Q0-Q15/A-1
FLASH
ARRAY
Y-PASS GATE
ARRAY
SOURCE
HV
SENSE
AMPLIFIER
PGM
DATA
HV
PROGRAM
DATA LATCH
STATE
REGISTER
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
AM: MSB address
P/N:PM1544
REV. 1.5, OCT. 30, 2013
8
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MX29GL256F equivalent, schematic
MX29GL256F
FUNCTIONAL OPERATION DESCRIPTION (cont'd)
READ SILICON ID MANUFACTURER CODE
To determine the Silicon ID Manufacturer Code, the system performs a READ OPERATION with A9 raised to
Vhv and address pins A6, A3, A2, A1, & A0 held LOW. The Macronix ID code of C2h should be present on data
bits Q7 to Q0.
READ INDICATOR BIT (Q7) FOR SECURITY SECTOR
To determine if the Security Sector has been locked at the factory, the system performs a READ OPERATION
with A9 raised to Vhv, address pin A6, A3 & A2 held LOW, and address pins A1 & A0 held HIGH. If the Security
Sector has been locked at the factory, the code 99h(H)/89h(L) will be present on data bits Q7 to Q0. Otherwise,
the factory unlocked code of 19h(H)/09h(L) will be present.
INHERENT DATA PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to Read mode during
power up. Additionally, the following design features protect the device from unintended data corruption.
COMMAND COMPLETION
Only after the successful completion of the specified command sets will the device begin its erase or program
operation. The failure in observing valid command sets will result in the memory returning to read mode.
LOW VCC WRITE INHIBIT
The device refuses to accept any write command when Vcc is less than VLKO. This prevents data from
spuriously being altered during power-up, power-down, or temporary power interruptions. The device
automatically resets itself when Vcc is lower than VLKO and write commands are ignored until Vcc is greater
than VLKO. The system must provide proper signals on control pins after Vcc rises above VLKO to avoid
unintentional program or erase operations.
WRITE PULSE "GLITCH" PROTECTION
CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write
cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at
Vih, WE# at Vih, or OE# at Vil.
P/N:PM1544
16
REV. 1.5, OCT. 30, 2013
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