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PDF ( 数据手册 , 数据表 ) MX25U6435E

零件编号 MX25U6435E
描述 FLASH MEMORY
制造商 MACRONIX
LOGO MACRONIX LOGO 


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MX25U6435E 数据手册, 描述, 功能
MX25U6435E
MX25U6435E
DATASHEET
P/N: PM1561
REV. 1.5, NOV. 07, 2013
1
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MX25U6435E pdf, 数据表
MX25U6435E
2. GENERAL DESCRIPTION
MX25U6435E is 67,108,864 bits serial Flash memory, which is configured as 8,388,608 x 8 internally. When it is
in two or four I/O mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. MX25U6435E feature a
serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O
mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial
access to the device is enabled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits
input and data output. When it is in four I/O read mode, the SI pin, SO pin and WP# pin become SIO0 pin, SIO1
pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25U6435E MXSMIO® (Serial Multi I/O) provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 30uA DC
current.
The MX25U6435E utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
P/N: PM1561
REV. 1.5, NOV. 07, 2013
8
http://www.Datasheet4U.com







MX25U6435E equivalent, schematic
MX25U6435E
8-1. Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in
command cycles, address cycles and as well as data output cycles.
Enable QPI mode
By issuing 35H command, the QPI mode is enabled.
Figure 2. Enable QPI Sequence (Command 35H)
CS#
SCLK
MODE 3
MODE 0
SIO0
SIO[3:1]
01 234567
35
P/N: PM1561
16
REV. 1.5, NOV. 07, 2013
http://www.Datasheet4U.com










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MACRONIX
MX25U6435FSERIAL MULTI I/O FLASH MEMORYMACRONIX
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