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零件编号 | MX25L51245G | ||
描述 | FLASH MEMORY | ||
制造商 | MACRONIX | ||
LOGO | |||
1 Page
PRELIMINARY
MX25L51245G
MX25L51245G
DATASHEET
P/N: PM2006
http://www.Datasheet4U.com
5. BLOCK DIAGRAM
SI/SIO0
CS#
WP#/SIO2
RESET#/SIO3
RESET pin
SCLK
SO/SIO1
PRELIMINARY
MX25L51245G
Address
Generator
Memory Array
Page Buffer
Data
Register
SRAM
Buffer
Mode
Logic
State
Machine
Y-Decoder
HV
Generator
Sense
Amplifier
Clock Generator
Output
Buffer
P/N: PM2006
REV. 0.01, JAN. 06, 2014
8
http://www.Datasheet4U.com
PRELIMINARY
MX25L51245G
Figure 6. EAR Operation Segments
03FFFFFFh
03000000h
EAR<1-0>= 11
02FFFFFFh
02000000h
EAR<1-0>= 10
01FFFFFFh
01000000h
EAR<1-0>= 01
00FFFFFFh
EAR<1-0>= 00
00000000h
When under EAR mode, Read, Program, Erase operates in the selected segment by using 3-byte address mode.
For the read operation, the whole array data can be continually read out with one command. Data output starts from
the selected top or bottom 128Mb, but it can cross the boundary. When the last byte of the segment is reached,
the next byte (in a continuous reading) is the first byte of the next segment. However, the EAR (Extended Address
Register) value does not change. The random access reading can only be operated in the selected segment.
The Chip erase command will erase the whole chip and is not limited by EAR selected segment. However, the
sector erase ,block erase , program operation are limited in selected segment and will not cross the boundary.
Figure 4. Write EAR Register (WREAR) Sequence (SPI Mode)
CS#
Mode 3
SCLK
Mode 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
command
EAR In
SI C5h 7 6 5 4 3 2 1 0
High-Z
MSB
SO
Figure 5. Write EAR Register (WREAR) Sequence (QPI Mode)
CS#
Mode 3
SCLK
Mode 0
SIO[3:0]
0 1 2 3 Mode 3
Command EAR in
Mode 0
C5h H0 L0
P/N: PM2006
16
REV. 0.01, JAN. 06, 2014
http://www.Datasheet4U.com
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页数 | 30 页 | ||
下载 | [ MX25L51245G.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
MX25L51245G | FLASH MEMORY | MACRONIX |
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