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零件编号 | MX25L25735F | ||
描述 | FLASH MEMORY | ||
制造商 | MACRONIX | ||
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1 Page
MX25L25735F
MX25L25735F
DATASHEET
P/N: PM1799
http://www.Datasheet4U.com
5. BLOCK DIAGRAM
Address
Generator
MX25L25735F
Memory Array
SI/SIO0
CS#
WP#/SIO2
HOLD#/SIO3
SCLK
SO/SIO1
Page Buffer
Data
Register
SRAM
Buffer
Mode
Logic
State
Machine
Y-Decoder
HV
Generator
Sense
Amplifier
Clock Generator
Output
Buffer
P/N: PM1799
REV. 1.2, OCT. 31, 2013
8
http://www.Datasheet4U.com
MX25L25735F
9. HOLD FEATURES
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start
until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial
Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial
Clock being low), see Figure below.
Figure 6. Hold Condition Operation
CS#
SCLK
HOLD#
Hold
Condition
(standard)
Hold
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care
during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of
the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
Figure 7. Hold Timing
CS#
SCLK
SO
HOLD#
tCHHL
tHLQZ
tHLCH
tCHHH
tHHCH
tHHQX
* SI is "don't care" during HOLD operation.
P/N: PM1799
16
REV. 1.2, OCT. 31, 2013
http://www.Datasheet4U.com
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页数 | 30 页 | ||
下载 | [ MX25L25735F.PDF 数据手册 ] |
零件编号 | 描述 | 制造商 |
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MX25L25735F | FLASH MEMORY | MACRONIX |
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