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PDF ( 数据手册 , 数据表 ) CYD18S36V18

零件编号 CYD18S36V18
描述 Dual Port SRAM
制造商 Cypress Semiconductor
LOGO Cypress Semiconductor LOGO 


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CYD18S36V18 数据手册, 描述, 功能
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
FullFlex™ Synchronous SDR
Dual Port SRAM
FullFlex™ Synchronous SDR Dual Port SRAM
Features
True dual port memory enables simultaneous access the
shared array from each port
Synchronous pipelined operation with single data rate (SDR)
operation on each port
SDR interface at 200 MHz
Up to 28.8 Gb/s bandwidth (200 MHz × 72-bit × 2 ports)
Selectable pipelined or flow-through mode
1.5 V or 1.8 V core power supply
Commercial and Industrial temperature
IEEE 1149.1 JTAG boundary scan
Available in 484-ball PBGA (× 72) and 256-ball FBGA (× 36
and × 18) packages
FullFlex72 family
36-Mbit: 512 K × 72 (CYD36S72V18)
18-Mbit: 256 K × 72 (CYD18S72V18)
9-Mbit: 128 K × 72 (CYD09S72V18)
FullFlex36 family
36-Mbit: 1 M × 36 (CYD36S36V18)
18-Mbit: 512 K × 36 (CYD18S36V18)
9-Mbit: 256 K × 36 (CYD09S36V18)
2-Mbit: 64 K × 36 (CYD02S36V18)
FullFlex18 family
36-Mbit: 2 M × 18 (CYD36S18V18)
18-Mbit: 1 M × 18 (CYD18S18V18)
9-Mbit: 512 K × 18 (CYD09S18V18)
Built in deterministic access control to manage address
collisions
Deterministic flag output upon collision detection
Collision detection on back-to-back clock cycles
First busy address readback
Advanced features for improved high speed data transfer and
flexibility
Variable impedance matching (VIM)
Echo clocks
Selectable LVTTL (3.3 V), Extended HSTL (1.4 V to 1.9 V),
1.8 V LVCMOS, or 2.5 V LVCMOS IO on each port
Burst counters for sequential memory access
Mailbox with interrupt flags for message passing
Dual chip enables for easy depth expansion
Functional Description
The FullFlex™ dual port SRAM families consist of 2-Mbit, 9-Mbit,
18-Mbit, and 36-Mbit synchronous, true dual port static RAMs
that are high speed, low power 1.8 V or 1.5 V CMOS. Two ports
are provided, enabling simultaneous access to the array.
Simultaneous access to a location triggers deterministic access
control. For FullFlex72 these ports operate independently with
72-bit bus widths and each port is independently configured for
two pipelined stages. Each port is also configured to operate in
pipelined or flow through mode.
The advanced features include the following:
Built in deterministic access control to manage address
collisions during simultaneous access to the same memory
location
Variable impedance matching (VIM) to improve data
transmission by matching the output driver impedance to the
line impedance
Echo clocks to improve data transfer
To reduce the static power consumption, chip enables power
down the internal circuitry. The number of latency cycles before
a change in CE0 or CE1 enables or disables the databus
matches the number of cycles of read latency selected for the
device. For a valid write or read to occur, activate both chip
enable inputs on a port.
Each port contains an optional burst counter on the input address
register. After externally loading the counter with the initial
address, the counter increments the address internally.
Additional device features include a mask register and a mirror
register to control counter increments and wrap around. The
counter interrupt (CNTINT) flags notify the host that the counter
reaches maximum count value on the next clock cycle. The host
reads the burst counter internal address, mask register address,
and busy address on the address lines. The host also loads the
counter with the address stored in the mirror register by using the
retransmit functionality. Mailbox interrupt flags are used for
message passing, and JTAG boundary scan and asynchronous
Master Reset (MRST) are also available. The Logic Block
Diagram on page 2 shows these features.
The FullFlex72 is offered in a 484-ball plastic BGA package. The
FullFlex36 and FullFlex18 are available in 256-ball fine pitch
BGA package except the 36-Mbit devices which are offered in
484-ball plastic BGA package.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06082 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 5, 2013
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CYD18S36V18 pdf, 数据表
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Figure 5. FullFlex18 SDR 256-ball BGA (Top View)
12
3
4
5 6 7 8 9 10 11 12 13 14 15 16
A DNU
DNU
DNU
DQ17L
DQ16L
DQ13L DQ12L DQ9L
DQ9R DQ12R
DQ13R
DQ16R
DQ17R
DNU
DNU
DNU
B DNU
C DNU
DNU
DNU
DNU
RETL
DNU
INTL
DQ15L
CQ1L
DQ14L
CQ1L
DQ11L
DNU
DQ10L
TRST
DQ10R DQ11R
MRST ZQ0R[17]
DQ14R
CQ1R
DQ15R
CQ1R
DNU
INTR
DNU
RETR
DNU
DNU
DNU
DNU
D A0L
A1L
WRPL
VREFL
FTSELL LOWSPDL VSS
VTTL
VTTL
VSS LOWSPDR FTSELR
VREFR
WRPR
A1R
A0R
E A2L
A3L
CE0L
CE1L
VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR
VDDIOR
CE1R
CE0R
A3R
A2R
F A4L
G A6L
A5L CNTINTL
A7L BUSYL
DNU
DNU
VDDIOL
ZQ0L[17]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
VDDIOR
DNU
DNU
CNTINTR
BUSYR
A5R
A7R
A4R
A6R
H A8L
A9L
CL
VTTL
VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VCORE
VTTL
CR
A9R
A8R
J A10L
A11L
VSS PORTSTD1L VCORE
VSS
VSS
VSS
VSS
VSS
VSS
VCORE PORTSTD1R VSS
A11R
A10R
K A12L
A13L
OEL
BE1L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
BE1R
OER
A13R
A12R
L A14L
A15L
ADSL
BE0L
VDDIOL
VSS
VSS
VSS
VSS
VSS
VSS
VDDIOR
BE0R
ADSR
A15R
A14R
M A16L
A17L
R/WL
N A18L[19] A19L[18] CNT/MSKL
CQENL
VDDIOL VDDIOL VDDIOL VCORE VCORE VDDIOR VDDIOR
VDDIOR
CQENR
VREFL PORTSTD0L READYL DNU
VTTL
VTTL
DNU
READYR PORTSTD0R VREFR
R/WR
A17R
A16R
CNT/MSKR A19R[18] A18R[19]
P DNU
DNU
CNTENL CNTRSTL
CQ0L
CQ0L
TCK
TMS
TDO
TDI
CQ0R
CQ0R
CNTRSTR CNTENR
DNU
DNU
R DNU
DNU
DNU
DNU
DQ6L
DQ5L
DQ2L
DQ1L
DQ1R
DQ2R
DQ5R
DQ6R
DNU
DNU
DNU
DNU
T DNU
DNU
DNU
DQ8L
DQ7L
DQ4L
DQ3L
DQ0L
DQ0R
DQ3R
DQ4R
DQ7R
DQ8R
DNU
DNU
DNU
Notes
17. Leave this ball unconnected to disable VIM.
18. Leave this ball unconnected for CYD09S18V18.
19. Leave this ball unconnected for CYD04S18V18.
Document Number: 38-06082 Rev. *O
Page 8 of 53







CYD18S36V18 equivalent, schematic
CYDXXS72V18
CYDXXS36V18
CYDXXS18V18
Figure 7. Counter, Mask, and Mirror Logic Block Diagram
Figure 7 shows the counter, mask, and mirror logic block diagram. [32]
CNT/MSK
CNTEN
A
CNTRST
RET
MRST
A
Decode
Logic
C
Mask
Register
Counter/
Address
Register
Address
Decode
RAM
Array
From
Address
Lines
20
From
Mask
Register
20
Load / Increment
Mirror
Increment
Logic Wrap
1
0
Counter
1
0
To Readback
and Address
Decode
20
From
Mask
From
Counter
20
20
+1
+2
+4
20
Bit 0
and 1
1
0
1
0
Wrap
Detect
20
Wrap
To Coun-
ter
Note
32. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and
CYD09S18V18 devices have 19 address bits. The CYD18S72V18 and CYD09S36V18 devices have 18 address bits. The CYD09S72V18 device has 17 address bits.
The CYD02S36V18 has 16 address bits.
Document Number: 38-06082 Rev. *O
Page 16 of 53
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