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PDF ( 数据手册 , 数据表 ) FL064P

零件编号 FL064P
描述 S25FL064P
制造商 Spansion
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FL064P 数据手册, 描述, 功能
S25FL064P
64-Mbit CMOS 3.0 Volt Flash Memory
with 104-MHz SPI (Serial Peripheral Interface) Multi I/O Bus
Data Sheet
S25FL064P Cover Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.
Publication Number S25FL064P_00
Revision 08
Issue Date January 29, 2013







FL064P pdf, 数据表
Data Sheet
Tables
Table 5.1
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 8.1
Table 8.2
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Table 9.7
Table 9.8
Table 9.9
Table 11.1
Table 13.1
Table 15.1
Table 16.1
Table 17.1
S25FL064P Valid Combinations Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Suggested Cross Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Configuration Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
TBPROT = 0 (Starts Protection from TOP of Array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
TBPROT=1 (Starts Protection from BOTTOM of Array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
S25FL064P Sector Address Table TBPARM=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
S25FL064P Sector Address Table TBPARM=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Manufacturer & Device ID - RDID (JEDEC 9Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Product Group CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Product Group CFI System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Product Group CFI Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Product Group CFI Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . .34
READ_ID Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
S25FL064P Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Power-Up / Power-Down Voltage and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
ACC Program Acceleration Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
DC Characteristics (CMOS Compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
8
S25FL064P
S25FL064P_00_08 January 29, 2013







FL064P equivalent, schematic
Data Sheet
7.7
7.8
Status Register
The Status Register contains the status and control bits that can be read or set by specific commands (see
Table 9.1 on page 23). These bits configure different protection configurations and supply information of
operation of the device. (for details see Table 9.8, S25FL064P Status Register on page 37):
Write In Progress (WIP): Indicates whether the device is performing a Write Registers, program or erase
operation.
Write Enable Latch (WEL): Indicates the status of the internal Write Enable Latch.
Block Protect (BP2, BP1, BP0): Non-volatile bits that define memory area to be software-protected
against program and erase commands.
Erase Error (E_ERR): The Erase Error Bit is used as an Erase operation success and failure check.
Program Error (P_ERR): The Program Error Bit is used as an program operation success and failure check.
Status Register Write Disable (SRWD): Places the device in the Hardware Protected mode when this bit
is set to 1 and the W#/ACC input is driven low. In this mode, the non-volatile bits of the Status Register
(SRWD, BP2, BP1, BP0) become read-only bits.
Configuration Register
The Configuration Register contains the control bits that can be read or set by specific commands. These bits
configure different configurations and security features of the device.
The FREEZE bit locks the BP2-0 bits in Status Register and the TBPROT and TBPARM bits in the
Configuration Register. Note that once the FREEZE bit has been set to 1, then it cannot be cleared to 0
until a power-on-reset is executed. As long as the FREEZE bit is set to 0, then the other bits of the
Configuration Register, including FREEZE bit, can be written to.
The QUAD bit is non-volatile and sets the pin out of the device to Quad mode; that is, W#/ACC becomes
IO2 and HOLD# becomes IO3. The instructions for Serial, Dual Output, and Dual I/O reads function as
normal. The W#/ACC and HOLD# functionality does not work when the device is set in Quad mode.
The TBPARM bit defines the logical location of the 4 kB parameter sectors. The parameter sectors consist
of thirty two 4 kB sectors. All sectors other than the parameter sectors are defined to be 64-kB uniform in
size. When TBPARM is set to a 1, the 4 kB parameter sectors starts at the top of the array. When TBPARM
is set to a 0, the 4 kB parameter sectors starts at the bottom of the array. Note that once this bit is set to a
1, it cannot be changed back to 0. The desired state of TBPARM must be selected during the initial
configuration of the device during system manufacture; before the first program or erase operation on the
main flash array. TBPARM must not be programmed after programming or erasing is done in the main flash
array.
The BPNV bit defines whether or not the BP2-0 bits in the Status Register are volatile or non-volatile.
When BPNV is set to a 1, the BP2-0 bits in the Status Register are volatile and will be reset to binary 111
after power on reset. When BPNV is set to a 0, the BP2-0 bits in the Status Register are non-volatile. Note
that once this bit is set to a 1, it cannot be changed back to 0.
The TBPROT bit defines the operation of the block protection bits BP2, BP1, and BP0 in the Status
Register. When TBPROT is set to a 0, then the block protection is defined to start from the top of the array.
When TBPROT is set to a 1, then the block protection is defined to start from the bottom of the array. Note
that once this bit is set to a 1, it cannot be changed back to 0. The desired state of TBPROT must be
selected during the initial configuration of the device during system manufacture; before the first program
or erase operation on the main flash array. TBPROT must not be programmed after programming or
erasing is done in the main flash array.
Note: It is suggested that the Block Protection & Parameter sectors not be set to the same area of the array;
otherwise, the user cannot utilize the Parameter sectors if they are protected. The following matrix shows the
recommended settings.
16
S25FL064P
S25FL064P_00_08 January 29, 2013










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