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PDF ( 数据手册 , 数据表 ) AD8139

零件编号 AD8139
描述 Differential ADC Driver
制造商 Analog Devices
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AD8139 数据手册, 描述, 功能
Data Sheet
FEATURES
Fully differential
Low noise
2.25 nV/√Hz
2.1 pA/√Hz
Low harmonic distortion
98 dBc SFDR at 1 MHz
85 dBc SFDR at 5 MHz
72 dBc SFDR at 20 MHz
High speed
410 MHz, 3 dB BW (G = 1)
800 V/µs slew rate
45 ns settling time to 0.01%
69 dB output balance at 1 MHz
80 dB dc CMRR
Low offset: ±0.5 mV maximum
Low input offset current: 0.5 µA maximum
Differential input and output
Differential-to-differential or single-ended-to-differential
operation
Rail-to-rail output
Adjustable output common-mode voltage
Wide supply voltage range: 5 V to 12 V
Available in a small SOIC package and an 8-lead LFCSP
APPLICATIONS
ADC drivers to 18 bits
Single-ended-to-differential converters
Differential filters
Level shifters
Differential PCB drivers
Differential cable drivers
GENERAL DESCRIPTION
The AD8139 is an ultralow noise, high performance differential
amplifier with rail-to-rail output. With its low noise, high
SFDR, and wide bandwidth, it is an ideal choice for driving
analog-to-digital converters (ADCs) with resolutions to 18 bits.
The AD8139 is easy to apply, and its internal common-mode
feedback architecture allows its output common-mode voltage
to be controlled by the voltage applied to one pin. The internal
feedback loop also provides outstanding output balance as well
as suppression of even-order harmonic distortion products. Fully
differential and single-ended-to-differential gain configurations
are easily realized by the AD8139. Simple external feedback
networks consisting of four resistors determine the closed-loop
gain of the amplifier.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Low Noise, Rail-to-Rail,
Differential ADC Driver
AD8139
FUNCTIONAL BLOCK DIAGRAMS
AD8139
–IN 1
VOCM 2
V+ 3
+OUT 4
8 +IN
7 NIC
6 V–
5 –OUT
NIC = NO INTERNAL CONNECTION.
Figure 1. 8-Lead SOIC
AD8139
TOP VIEW
(Not to Scale)
–IN 1
VOCM 2
V+ 3
+OUT 4
8 +IN
7 NIC
6 V–
5 –OUT
NIC = NO INTERNAL CONNECTION.
Figure 2. 8-Lead LFCSP
The AD8139 is manufactured on the proprietary Analog Devices,
Inc., second-generation XFCB process, enabling it to achieve low
levels of distortion with input voltage noise of only 2.25 nV/√Hz.
The AD8139 is available in an 8-lead SOIC package with an
exposed paddle (EP) on the underside of its body and a 3 mm ×
3 mm LFCSP. It is rated to operate over the temperature range
of −40°C to +125°C.
100
10
1
10 100 1k 10k 100k 1M 10M 100M 1G
FREQUENCY (Hz)
Figure 3. Input Voltage Noise vs. Frequency
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com







AD8139 pdf, 数据表
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
VOCM
Power Dissipation
Input Common-Mode Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rating
12 V
±VS
See Figure 4
±VS
−65°C to +125°C
−40°C to +125°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4.
Package Type
8-Lead SOIC with EP/4-Layer
8-Lead LFCSP/4-Layer
θJA Unit
70 °C/W
70 °C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8139 package
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8139. Exceeding a junction temperature
of 175°C for an extended period can result in changes in the
silicon devices potentially causing failure.
AD8139
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
the internal common-mode feedback loop. The internal resistor
tap used in the common-mode feedback loop places a 1 kΩ
differential load on the output. RMS output voltages should be
considered when dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduce the θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
(EP) 8-lead SOIC (θJA = 70°C/W) and the 8-lead LFCSP
JA = 70°C/W) on a JEDEC standard 4-layer board. θJA
values are approximations.
4.0
3.5
3.0
2.5
2.0
1.5
SOIC
AND LFCSP
1.0
0.5
0
–40 –20
0
20 40 60 80 100 120
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. C | Page 7 of 26







AD8139 equivalent, schematic
Data Sheet
0 RL, dm = 1k
–10 PSRR = VO, dm/VS
–20
–30
–40
–PSRR
–50
+PSRR
–60
–70
–80
–90
–100
1
10
FREQUENCY (MHz)
100
Figure 43. PSRR vs. Frequency
500
100
VS = +5V
10
VS = ±5V
1
0.1
0.01
0.1
1 10 100
FREQUENCY (MHz)
1000
Figure 44. Single-Ended Output Impedance vs. Frequency
700
600
500
400
300
200
100
0
–100
VS = ±5V
–200
–300
–400
–500
–600
–700
100
VS = +5V
VS+ – VOP
VON – VS–
1k
RESISTIVE LOAD ()
10k
Figure 45. Output Saturation Voltage vs. Output Load
AD8139
14 G = 2
12
10
8
6
4
2
0
–2
–4
–6
–8
–10
–12
–14
2 × VIN, dm
VO, dm
TIME (ns)
Figure 46. Overdrive Recovery
50ns/DIV
0 VO, dm = 1V p-p
–10 OUTPUT BALANCE = VO, cm/VO, dm
–20
–30
–40
–50
–60
–70
–80
1
10
FREQUENCY (MHz)
100
Figure 47. Output Balance vs. Frequency
500
300
VS = ±5V
G = 1 (RF = RG = 200)
RL, dm = 1k
250
200
VS+ – VOP
–50
–100
–150
150 –200
VON – VS–
100 –250
50
–40
–20 0
–300
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 48. Output Saturation Voltage vs. Temperature
Rev. C | Page 15 of 26










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