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PDF ( 数据手册 , 数据表 ) HCPL-0720

零件编号 HCPL-0720
描述 CMOS Optocoupler
制造商 Agilent
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HCPL-0720 数据手册, 描述, 功能
Agilent
HCPL-0720/7720 and HCPL-0721/7721
40 ns Propagation Delay,
CMOS Optocoupler
Data Sheet
Description
Available in either an 8-pin DIP or
SO-8 package style respectively, the
HCPL-772X or HCPL-072X
optocouplers utilize the latest
CMOS IC technology to achieve
outstanding performance with very
low power consumption. The
HCPL-772X/072X require only two
bypass capacitors for complete
CMOS compatability.
Basic building blocks of the
HCPL-772X/072X are a CMOS
LED driver IC, a high speed LED
and a CMOS detector IC. A CMOS
logic input signal controls the
LED driver IC which supplies
current to the LED. The detector
IC incorporates an integrated
photodiode, a high-speed
transimpedance amplifier, and a
voltage comparator with an
output driver.
Functional Diagram
**VDD1 1
VI 2
*3
GND1 4
LED1
SHIELD
8 VDD2**
7 NC*
IO
6 VO
5 GND2
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
* Pin 3 is the anode of the internal LED and must be left unconnected for
guaranteed data sheet performance. Pin 7 is not connected internally.
**A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and
5 and 8.
Features
• +5 V CMOS compatibility
• 20 ns maximum prop. delay skew
• High speed: 25 MBd
• 40 ns max. prop. delay
• 10 kV/µs minimum common mode
rejection
• –40 to 85°C temperature range
• Safety and regulatory approvals
UL recognized
3750 V rms for 1 min. per
UL 1577
CSA component acceptance
notice #5
IEC/EN/DIN EN 60747-5-2
– VIORM = 630 Vpeak for
HCPL-772X option 060
– VIORM = 560 Vpeak for
HCPL-072X option 060
Applications
• Digital fieldbus isolation: CC-Link,
DeviceNet, Profibus, SDS
• AC plasma display panel level
shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
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HCPL-0720 pdf, 数据表
Package Characteristics
Parameter
Input-Output Momentary
Withstand Voltage
072X
772X
Resistance
(Input-Output)
Capacitance
(Input-Output)
Input Capacitance
Input IC Junction-to-Case
Thermal Resistance
Output IC Junction-to-Case
Thermal Resistance
Package Power Dissipation
-772X
-072X
-772X
-072X
Symbol
VISO
Min.
3750
3750
RI-O
Typ. Max. Units
Vrms
1012
Test Conditions
RH 50%,
t = 1 min.,
TA = 25°C
VI-O = 500 Vdc
Fig. Note
8, 9,
10
8
CI-O 0.6 pF f = 1 MHz
CI 3.0
11
θjci 145 °C/W Thermocouple
160 located at center
θjco 140
135
underside of package
PPD 150 mW
Notes:
1. Absolute Maximum ambient operating
temperature means the device will not be
damaged if operated under these conditions.
It does not guarantee functionality.
2. The LED is ON when VI is low and OFF when
VI is high.
3. tPHL propagation delay is measured from the
50% level on the falling edge of the VI signal
to the 50% level of the falling edge of the VO
signal. tPLH propagation delay is measured
from the 50% level on the rising edge of the
VI signal to the 50% level of the rising edge of
the VO signal.
4. PWD is defined as |tPHL - tPLH|.
%PWD (percent pulse width distortion) is
equal to the PWD divided by pulse width.
5. tPSK is equal to the magnitude of the worst
case difference in tPHL and/or tPLH that will
be seen between units at any given
temperature within the recommended
operating conditions.
6. CMH is the maximum common mode voltage
slew rate that can be sustained while
maintaining VO > 0.8 VDD2. CML is the
maximum common mode voltage slew rate
that can be sustained while maintaining
VO < 0.8 V. The common mode voltage slew
rates apply to both rising and falling common
mode voltage edges.
7. Unloaded dynamic power dissipation is
calculated as follows: CPD * VDD2 * f + IDD *
VDD, where f is switching frequency in MHz.
8. Device considered a two-terminal device:
pins 1, 2, 3, and 4 shorted together and pins
5, 6, 7, and 8 shorted together.
9. In accordance with UL1577, each HCPL-072X
is proof tested by applying an insulation test
voltage 4500 VRMS for 1 second (leakage
detection current limit, II-O 5 µA). Each
HCPL-772X is proof tested by applying an
insulation test voltage 4500 Vrms for 1
second (leakage detection current limit.
II-O 5 µA.)
10. The Input-Output Momentary Withstand
Voltage is a dielectric voltage rating that
should not be interpreted as an input-output
continuous voltage rating. For the continuous
voltage rating refer to your equipment level
safety specification or Agilent Application
Note 1074 entitled “Optocoupler Input-Output
Endurance Voltage.”
11. CI is the capacitance measured at pin 2 (VI).
5
4
3
2
1
0
01
0 °C
25 °C
85 °C
2 3 45
VI (V)
Figure 1. Typical output voltage vs. input
voltage.
2.2
2.1
2.0
1.9
1.8
1.7
1.6
4.5
0 °C
25 °C
85 °C
4.75 5 5.25
VDD1 (V)
5.5
29
27
25
TPLH
23
21 TPHL
19
17
15
0 10 20 30 40 50 60 70 80
TA (C)
Figure 2. Typical input voltage switching
threshold vs. input supply voltage.
Figure 3. Typical propagation delays vs.
temperature.
8
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HCPL-0720 equivalent, schematic
Power Supplies and Bypassing
The recommended DeviceNet
application circuit is shown in
Figure 21. Since the HCPL-772X/
072X are fully compatible with
CMOS logic level signals, the
optocoupler is connected directly
to the CAN transceiver. Two
bypass capacitors (with values
between 0.01 and 0.1 µF) are
required and should be located as
close as possible to the input and
output power-supply pins of the
HCPL-772X/072X. For each
capacitor, the total lead length
between both ends of the
capacitor and the power supply
pins should not exceed 20 mm.
The bypass capacitors are
required because of the high-
speed digital nature of the signals
inside the optocoupler.
ISO 5 V
GALVANIC
ISOLATION
BOUNDARY
TX0
0.01 µF
1 VDD1
VDD2 8
2 VIN
7
HCPL-772x
3 HCPL-072x VO 6
4 GND1
GND2 5
GND
RX0
0.01 µF
5 GND2
GND1 4
6 VO
3
HCPL-772x
7 HCPL-072x VIN 2
0.01
µF
0.01
µF
5V
LINEAR OR
SWITCHING
REGULATOR
+
VCC
TxD
CANH
+
C4
0.01 µF
82C250
CANL
Rs REF
RXD
GND
VREF
D1
30 V
+
5 V+
4 CAN+
3 SHIELD
2 CAN
1 V
C1
0.01 µF
500 V
R1
1M
8 VDD2
ISO 5 V
VDD1 1
5V
Figure 21. Recommended DeviceNet application circuit.
Implementing PROFIBUS with the
HCPL-772X/072X
An acronym for Process Fieldbus,
PROFIBUS is essentially a twisted-
pair serial link very similar to RS-
485 capable of achieving high-speed
communication up to 12 MBd. As
shown in Figure 22, a PROFIBUS
Controller (PBC) establishes the
connection of a field automation
unit (control or central processing
station) or a field device to the
transmission medium. The PBC
consists of the line transceiver,
optical isolation, frame character
transmitter/receiver (UART), and
the FDL/APP processor with the
interface to the PROFIBUS user.
PROFIBUS USER:
CONTROL STATION
(CENTRAL PROCESSING)
OR FIELD DEVICE
PBC
USER INTERFACE
FDL/APP
PROCESSOR
UART
OPTICAL ISOLATION
MEDIUM
TRANSCEIVER
Figure 22. PROFIBUS Controller (PBC).
16
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